Seung-Min Jung

Thinning Processor for 160 X 192 Pixel Array Fingerprint Recognition

A thinning algorithm changes a binary fingerprint image to one pixel width. A thinning stage occupies 40% cycle of 32-bit RISC microprocessor system for a fingerprint identification algorithm. Hardware block processing is more effective than software one in speed, because a thinning algorithm is iteration of simple instructions. This paper describes an effective hardware scheme for thinning stage processing using the Verilog-HDL in 160x192 Pixel Array. The ZS algorithm was applied for a thinning stage. The hardware scheme was designed and simulated in RTL. The logic was also synthesized by XST in FPGA environment. Experimental results show the performance of the proposed scheme.

Design of Low Power Capacitive Sensing Circuit with a High Resolution in CMOS Technology

This paper describes the possibility of a lowpower, high-resolution fingerprint sensor chip. A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than conventional circuit. The detection circuit is designed and simulated in 3.3V, 0.35μm standard CMOS process, 40MHz condition. The result shows about 27% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is more stable and effective than a typical circuit.

An ASIC Implementation of Fingerprint Thinning Algorithm

716 Seung-Min Jung : AN ASIC IMPLEMENTATION OF FINGERPRINT THINNING ALGORITHM Abstract—This paper proposes an effective fingerprint identification system with hardware block for thinning stage processing of a verification algorithm based on minutiae with 39% occupation of 32-bit RISC microprocessor cycle. Each step of a fingerprint algorithm is analyzed based on FPGA and ARMulator. This paper designs an effective hardware scheme for thinning stage processing using the Verilog-HDL in 160x192 pixel array. The ZS algorithm is applied for a thinning stage. The logic is also synthesized in 0.35µm 4-metal CMOS process. The layout is performed based on an auto placement-routing and post-simulation is performed in logic level. The result is compared with a conventional one. Index Terms— ASIC, Verilog-HDL, thinning, fingerprint, RTL, VLSI,

A Parasitic-Insensitive Charge Transfer Circuit for Capacitive Sensing Based on Switched Capacitor Integrator

This paper introduces a parasitic-insensitive charge transfer circuit based on a switched capacitor integrator. The parasitic-insensitive charge transfer circuit includes four switches to eliminate parasitic capacitance. The degradation of sensitivity caused from parasitic capacitance was simulated with standard 0.35 μm CMOS technology and compared with that of a parasitic-sensitive charge transfer circuit. It can be concludes from the results, that even without the need of complicated circuits and additional touch schemes, the parasitic-insensitive can be effectively used in capacitive sensing for touch devices, such as a touch screen panel.

A Study of a High Performance Capacitive Sensing Scheme Using a Floating-Gate MOS Transistor

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 μm standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.