Morgan Whately

Standby power reduction and SRAM cell optimization for 65nm technology

Standby power is one of the most critical issues in low power chip applications. In this paper, we have investigated the effects of body bias and source bias in 65nm technology through simulations on SRAM standby current (Isb). The simulation results show a 8X reduction in cell Isb at 125°C FF process corner with a 1.0V NMOS body bias. This has been experimentally verified on a 16Mb SRAM testchip. Source biasing is shown to be a more effective technique for room temperature leakage reduction (~3X lower Isb@0.4V bias). Optimizing the SRAM cell is crucial to meet the product performance requirements across corners and a methodology for the same is also described. The 16Mb testchip was characterized for read disturb, write margin and read current margin at process corners by applying forward and reverse body biases to shift the cell transistor parameters. Different test sequences tailored for the parameter being measured were used to determine the failing bit count in each case. Voltage schmoo plots were generated from the measured data to obtain the Vccmin at each body bias condition. Based on the above, the threshold voltages of the cell transistors for maximum operating margin were derived.

A novel OTA-based fast lock PLL

This paper describes a novel fast lock scheme for phase-locked loops (PLLs). The proposed scheme uses a simple operational transconductance amplifier (OTA) to achieve significant reduction in PLL lock acquisition time without affecting PLL noise performance. The new scheme allows short starting time and fast dynamic power cycling for various subsystems on SOCs. Multiple PLLs utilizing the new fast lock schemes were implemented in multi-port SRAM chip to provide frequencies from 400MHz to 1.6GHz, The chip was fabricated using 65nm CMOS process. Silicon measurements across corner lots show significant reduction in PLL lock time, by a factor of 6.5X, over device operating conditions.

A novel switched-capacitor-filter based low-area and fast-locking PLL

A new low-area and fast-locking Phase Locked Loop (PLL) is presented. The proposed PLL employs a new switched capacitor (SC) filter that uses fractional charge integration to implement capacitor multiplication effect. The proposed (SC) filter has a time response similar to the traditional passive filter response while occupying much smaller area and without any impact on other PLL blocks design. The proposed PLL was built in a 65nm CMOS process with a capacitance multiplication factor of 16 in parallel with a traditional filter for performance comparison. The PLL has an operating frequency range of 200MHz to 2.0GHz. Using a ring oscillator the PLL has period jitter in the order of 0.9ps RMS with acquisition time less than 10uS. Traditional LPF area is 180μm × 340μm while the (SC) LPF area is only 104μm × 84μm cutting LPF area by a factor 7.

Directions in future of SRAM with QDR-WideIO for high performance networking applications and beyond

In this paper we describe the high performance synchronous QDR-WideIO SRAM KGD from Cypress that is architected with fast and wide interface with optimized memory sub-system for future high performance networking and computing applications. Systems for next generation networking switches rely on high rate router line cards of 200 to 400 Gbps. QDR-WideIO fabricated on 28nm HKMG technology builds upon High Bandwidth Memory (HBM) interface standard while using 2.5D/3D stacking to form a System in Package (SiP) networking system solutions. We explain that both SRAM and DRAM are necessary and can co-exist in these systems and why it does not make sense to integrate the SRAM inside the logic ASIC. We also describe the memory design and partitioning that allows for delivering requisite Random Transaction Rate (RTR) representing random accesses to the memory per second of approaching 24000 MT/s (>10X improvement over our previous generation of QDR-IV synchronous SRAM) and total bandwidth of greater than 1.5 Tbps in a power efficient way. QDR-WideIO achieves latency of 13 cycles for read and 8 cycles for write with density of 288Mb with core operating at 1500 MHz. Finally we describe a path forward toward future of in-package integrated products.