Joseph Tzou

Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses

Memory device and method

Method and apparatus for built-in self-test (BIST) of integrated circuit device

Circuit and method for cascading programmable impedance matching in a multi-chip system

Access methods and circuits for memory devices having multiple banks

Single late-write for standard synchronous SRAMs

Circuits and methods for programming integrated circuit input and output impedances

Memory device data latency circuits and methods

Area efficient and fast static random access memory circuit and method

Memory array with current limiting device for preventing particle induced latch-up