Morimi Osawa

Proximity effect correction using pattern shape modification and area density map for electron-beam projection lithography

A novel proximity effect correction algorithm using pattern shape modification and the area density map method for electron-beam projection lithography is proposed. This algorithm enables fast, accurate and self-consistent calculation of modified pattern sizes. The correctable minimum feature sizes for shape modification were investigated from two viewpoints, mask fabrication restriction and dose margin. The correctable minimum sizes are mostly determined by the dose margin requirement in the case of isolated and dense repeated patterns, implying that the tool resolution determines correctable minimum sizes. A special technique is required for isolated space patterns where the backscattering energy cannot be reduced by simple sizing. We have implemented an algorithm in which pattern densities at middle parts of large patterns are reduced by using a lines and spaces (L/S) pattern or mesh patterns for that case. Successful correction results down to 60 nm from the simulation and 100 nm from the experiment have been obtained.

Correction for local flare effects approximated with double Gaussian profile in ArF lithography

A method has been developed for correcting line width variations due to midrange flare with a scattering range of over a few tens of micrometers (which we call local flare). It is shown that the conventional single Gaussian point spread function (PSF) is not sufficient and that a double Gaussian point spread function is needed to explain the line width variation caused by local flare. The remaining errors after correction are discussed under the assumptions that the mask correction is linear with respect to local flare intensity and is independent of pattern layout considering the order of the local flare correction (LFC) and optical proximity correction (OPC). This simple sizing method can reduce the critical dimension (CD) variation regardless of whether LFC is done before or after OPC. The LFC performance was evaluated using actual 90-nm-node LSI data. A much faster correction time than that of OPC was achieved by introducing the area density map method. The CD variation due to local flare was reduced from 22 to 5 nm.

Proximity effect correction using pattern shape modification and area density map

A proximity effect correction program in which forward scattering is corrected by shape modification and backscattering is corrected by dose modulation is developed. The amount of the shape modification is determined in such a manner that the full width at half maximum of the forward scattering profile is equal to the designed size. The half maximum of the forward scattering profile is equalized by the dose modulation after the amount of the backscattering is evaluated by the area density map method. This algorithm automates pattern biasing to improve the resolution and assures the resulting pattern size is as designed. The following features are included to improve the conventional methods: The area density map is smoothed iteratively to include higher order effect. Smaller meshes are used for better discretization accuracy. Auxiliary shots are generated to refine correction units where the spatial profile of the deposited energy is steep. The corrected results of 60 nm lines are also presented.

Three-Dimensional Proximity Effect Correction for Multilayer Structures in Electron Beam Lithography

Proximity effects in multiwiring layers including heavy-metal materials such as tungsten (W) plug are crucial. In this paper, a novel three-dimensional proximity effect correction method which is based on the simplified electron energy flux (SEEF) model combined with the extended area density map method to multilayer structure is proposed. In this SEEF model, electron energy fluxes transmitted and reflected at each layer are discussed and their maps are reconstructed repeatedly by distributing and gathering electron energy fluxes at each layer. The resultant final map of electron energy flux at the surface layer under the resist contributes as the backscattering energy deposited in the resist. Our new correction method has been confirmed by the experiments to powerfully correct the proximity effects in a 3-layer structure. The screening effect due to the W plug array is first observed and can also be corrected by the proposed method.

3D proximity effect correction based on the simplified electron energy flux model in electron-beam lithography

We have confirmed the adequacy of simplified electron energy flux (SEEF) model which can be used in proximity effect correction (PEC) in electron beam lithography. The SEEF model enables calculation of the backscattering energy in a multiwiring structure by obtaining a transmission and reflection energy flux map. We prepared a substrate which contained three pairs of W-plug layers and inter-metal dielectric (IMD) layers, and obtained parameters for correction. The extracted transmittance and reflectance were 1 and 0 for the dielectrics, and 0 and 1.7 for the W plugs. The backscattering energies calculated by using these parameters corresponded with experimental data under the various conditions. We also extracted the scattering range of incident and reflected electrons in dielectrics. We found that the ranges of the reflected electrons were greater than those of the incident electrons because of a wider spread of angle. PEC based on the SEEF model enabled high CD accuracy even at the end of the W-plug are...

Model-based OPC/DRC considering local flare effects

Local flare is caused by scattered light from lens surfaces, and it causes the printed line width to vary or degrades printing accuracy. Consequently, local flare must be taken into account when manufacturing IC devices that use lithography generations of less than 90 nm. In particular, an OPC (Optical Proximity Correction) tool with the ability to compensate local flare effects is required to maintain a high degree of printing accuracy. For model-based OPC to work properly, the predicted line width or shape given by a simulator should show good agreement with experimental results. Local flare intensity is calculated from the optical intensity in the absence of local flare, in order to take diffraction effects into account. An aerial image considering local flare effects is given simply by the sum of optical intensity and local flare intensity. To account for local flare effects in a practical manner, the local flare intensity is converted into a variation in the threshold for OPC/DRC (Design Rules Checking) that predicts the desired shape. This paper describes the impact of local flare, the simulation model including local flare effects, and its results. The simulation results show good agreement with the experimental results, indicating that effective OPC/DRC using this method is possible.

High-speed proximity effect correction system for electron-beam projection lithography by cluster processing

We have proposed the techniques of the pattern shape modification method and the pattern density reduction method as a proximity effect correction (PEC) for electron-beam projection lithography.

High-performance proximity effect correction for sub-70 nm design rule system on chip devices in 100 kV electron projection lithography

The proximity effect correction (PEC) system to achieve the practical processing time and data volume for sub-65 nm design-rule system on chip (SoC) devices is improved. The lump method, which is the technique to process several subfields at a time, is used to reduce the processing time for PEC. The hierarchical data processing for PEC is also proposed to reduce the data volume. A PC cluster system has been used to reduce the processing time for PEC. For an actual 70 nm design-rule SoC device data, the processing time has been reduced from 7.8 h to 10.3 min and the data volume has been reduced from 12.4 to 2.6 GB by using the lump method, the hierarchical data processing, and a ten PC cluster system. And, we have confirmed that the required critical dimension accuracy of ±5% is achieved for the device data in the simulation. We have successfully fabricated a full-size 8 in. Si stencil mask using the data with our PEC system for an actual 70 nm design-rule SoC device.

Fast and Simplified Technique of Proximity Effect Correction for Ultra Large Scale Integrated Circuit Patterns in Electron-Beam Projection Lithography

The pattern shape modification method is an effective proximity effect correction technique for electron-beam projection lithography (EPL) systems. We used two characteristics based on the large difference between the forward and backscattering ranges of incident electrons from the 100 kV EPL system to simplify and speed up the pattern shape modification method. The first characteristic is that the amount of pattern bias becomes almost identical on opposite sides of a sufficiently small pattern compared to the backscattering range. The second characteristic is that although the equations for calculating the amount of pattern bias are simultaneous equations, they can be solved separately if the pattern is sufficiently long compared to the forward-scattering range. In addition, multithreading was used to perform parallel processing for the purpose of speeding up the pattern shape modification method. This simplification and speeding up cut the processing time to 1/3 when using four processors. We also checked the correction accuracy by repetition, and considered the use of a correction that maintains the hierarchy for compressing the amount of data.

Practical proof of CP element based design for 14nm node and beyond

To realize HVM (High Volume Manufacturing) with CP (Character Projection) based EBDW, the shot count reduction is the essential key. All device circuits should be composed with predefined character parts and we call this methodology “CP element based design”. In our previous work, we presented following three concepts [2]. 1) Memory: We reported the prospects of affordability for the CP-stencil resource. 2) Logic cell: We adopted a multi-cell clustering approach in the physical synthesis. 3) Random interconnect: We proposed an ultra-regular layout scheme using fixed size wiring tiles containing repeated tracks and cutting points at the tile edges. In this paper, we will report the experimental proofs in these methodologies. In full chip layout, CP stencil resource management is critical key. From the MCC-POC (Proof of Concept) result [1], we assumed total available CP stencil resource as 9000um2. We should manage to layout all circuit macros within this restriction. Especially the issues in assignment of CP-stencil resource for the memory macros are the most important as they consume considerable degree of resource because of the various line-ups such as 1RW-, 2RW-SRAMs, Resister Files and ROM which require several varieties of large size peripheral circuits. Furthermore the memory macros typically take large area of more than 40% of die area in the forefront logic LSI products so that the shot count increase impact is serious. To realize CP-stencil resource saving we had constructed automatic CP analyzing system. We developed two types of extraction mode of simple division by block and layout repeatability recognition. By properly controlling these models based upon each peripheral circuit characteristics, we could minimize the consumption of CP stencil resources. The estimation for 14nm technology node had been performed based on the analysis of practical memory compiler. The required resource for memory macro is proved to be affordable value which is 60% of full CP stencil resource and wafer level converted shot count is proved to be the level which meets 100WPH throughput. In logic cell design, circuit performance verification result after the cell clustering has been estimated. The cell clustering by the acknowledgment of physical distance proved to owe large penalty mainly in the wiring length. To reduce this design penalty, we proposed CP cell clustering by the acknowledgment of logical distance. For shot-count reduction of random interconnect area design, we proposed a more structural routing architecture which consists of the track exchange and the via position arrangement. Putting these design approaches together, we can design CP stencils to hit the target throughput within the area constraint. From the analysis for other macros such as analog, I/O, and DUMMY, it has proved that we don’t need special CP design approach than legacy pattern matching CP extraction. From all these experimental results we get good prospects to the reality of full CP element based layout.