Teruyoshi Yao

New double exposure technique without alternating phase-shift mask

The double exposure technique using alternating phase shift mask (alt-PSM) has been proposed and it is well used for the gate layer of the high performance logic devices as strong resolution enhancement technology (RET). This technique has advantage that the fine resist profile is obtained on wafer with extensive process margin. However, this double exposure technique is very expensive because of the alt-PSM cost. This time, the new double exposure technique without alt-PSM is developed for gate layer of 45 nm node logic devices. In this new double exposure method, attenuated phase shift mask (att-PSM) or binary mask (BIM) is used with dipole illumination. It is thought that this new double exposure method is effective for random logic devices which have various pattern pitches by the optimization of dipole illumination condition and pattern placement. Firstly, the optical contrast and depth of focus (DOF) is calculated. From these results, dipole illumination condition is optimized. It is found that DOF of new double exposure method is wider than that of conventional method. In addition, mask pattern is optimized to obtain wide process margin. For dense pattern, mask biasing is effective and optimization of shifter width is effective for isolated pattern. Furthermore, it is found that assist pattern is very effective for isolated pattern. From experimental results, it is proved that new double exposure method have wider process margin than that of conventional one. The strong design for manufacturing (DFM) rule that required the severe line width control is placed at single direction is proposed to realize the new double exposure method. Finally, it is found that the lithographic performance of new double exposure method has same level as conventional method with alt-PSM for gate layer of 45 nm logic devices.

Correction for local flare effects approximated with double Gaussian profile in ArF lithography

A method has been developed for correcting line width variations due to midrange flare with a scattering range of over a few tens of micrometers (which we call local flare). It is shown that the conventional single Gaussian point spread function (PSF) is not sufficient and that a double Gaussian point spread function is needed to explain the line width variation caused by local flare. The remaining errors after correction are discussed under the assumptions that the mask correction is linear with respect to local flare intensity and is independent of pattern layout considering the order of the local flare correction (LFC) and optical proximity correction (OPC). This simple sizing method can reduce the critical dimension (CD) variation regardless of whether LFC is done before or after OPC. The LFC performance was evaluated using actual 90-nm-node LSI data. A much faster correction time than that of OPC was achieved by introducing the area density map method. The CD variation due to local flare was reduced from 22 to 5 nm.

Challenging to meet 1nm iso-dense bias (IDB) by controlling laser spectrum

According to the ITRS Roadmap, for 45nm Node (as 65nm Half Pitch), the requirement of Gate CD Control is defined as 2.6nm. One of the most challenging CD errors is Iso-Dense Bias (IDB). Assuming 40% of CD errors are dominated by IDB, IDB should be less than 1nm. In general, the majority of IDB is due to: primarily, exposure tool- related factors such as aberrations, flare, and sigma fluctuation, and secondly, the change in photoresist characteristics. However, due to the rapidly increasing usage of ArF exposure tools, Band Width (BW) characteristics of the laser source is an additional factor whose contribution is becoming more critical. Ideally, BW is monochromatic, thereby not affected by chromatic aberration change. However, in reality, the BW exhibits a shape of spectral distribution with a finite width. This study describes experimental and simulation results for E95%, and how performance of both CDs and Laser is dependent on E95% in order to meet 1nm of IDB towards 45nm Node. -IDB vs. E95% -CD at through pitch vs. E95% -Process Latitude vs. E95% -DOF -EL -Pattern shortening vs. E95%

Joint optimization of layout and litho for SRAM and logic towards the 20nm node using 193i

This paper reports on a simulation study in which we compare different possibilities to find a litho solution for SRAM and Logic for planar technology nodes between 28 nm and 20 nm, using 193 nm immersion lithography. At these nodes, it becomes essential to include the layout itself into the optimization process. The so-called gridded layout style is an attractive candidate to facilitate the printability of several layers, but the benefit of this style, as compared to less restricted layout styles, is not well quantified for the various technology nodes of interest. We therefore compare it with two other, less restricted, layout styles, on an identical (small) SRAM-Logic test chip. Exploring a number of paths in the layout-style - litho-options search space, we try to quantify merits and trade-offs for some of the relevant options. We will show that layout restrictions are really becoming mandatory for the technology nodes studied in this paper. Other important enablers for these aggressive nodes are multiple patterning, the use of a local-interconnect layer, negative-tone development, SMO and the use of optimized free-form illumination sources (from which we also include a few initial wafer results).

Model-based OPC/DRC considering local flare effects

Local flare is caused by scattered light from lens surfaces, and it causes the printed line width to vary or degrades printing accuracy. Consequently, local flare must be taken into account when manufacturing IC devices that use lithography generations of less than 90 nm. In particular, an OPC (Optical Proximity Correction) tool with the ability to compensate local flare effects is required to maintain a high degree of printing accuracy. For model-based OPC to work properly, the predicted line width or shape given by a simulator should show good agreement with experimental results. Local flare intensity is calculated from the optical intensity in the absence of local flare, in order to take diffraction effects into account. An aerial image considering local flare effects is given simply by the sum of optical intensity and local flare intensity. To account for local flare effects in a practical manner, the local flare intensity is converted into a variation in the threshold for OPC/DRC (Design Rules Checking) that predicts the desired shape. This paper describes the impact of local flare, the simulation model including local flare effects, and its results. The simulation results show good agreement with the experimental results, indicating that effective OPC/DRC using this method is possible.

Novel Optimization of Total Alignment Error Factors.

A novel optimization method has been developed for reducing total alignment error. We have investigated alignment errors induced by the interaction between the exposure tool and the wafer process, including measurement methodologies. We discovered that the chromatic image shift (CIS) in image processing alignment sensors has a strong effect on the alignment offset in processed wafers. The minimization of alignment offsets between various layers has been achieved. This improvement is realized by: (1) measuring the CIS as a measurement offset between two different illumination wavelengths on an alignment mark of an etched silicon step whose height is λ/8, where λ is the averaged illumination wavelength; (2) adopting electrical measurement to verify alignment accuracy; (3) clarifying the relationship between the CIS and alignment offsets of actual devices to obtain the tolerance of CIS; (4) adjusting optical elements of the alignment system to suppress CIS within tolerance; and (5) determining which alignment marks will induce the smallest alignment offset. This methodology contributes significantly to process automation and the elimination of the need for a send-ahead wafer.

In-line-focus monitoring technique using lens aberration effect

Process windows have become narrower as nano-processing technology has advanced. The semiconductor industry, faced with this situation, has had to impose extremely severe tool controls. Above all, with the advent of 90-nm device production, demand has arisen for strict levels of control that exceed the machine specifications of ArF exposure systems. Consequently, high-accuracy focus control and focus monitoring techniques for production wafers will be necessary in order for this to be achieved for practical use. Focus monitoring techniques that measure pattern placement errors and resist features using special reticle and mark have recently been proposed. Unfortunately, these techniques have several disadvantages. They are unable to identify the direction of a focus error, and there are limits on the illumination conditions. Furthermore, they require the use of a reticle that is more expensive than normal and they suffer from a low level of measurement accuracy. To solve these problems, the authors examined methods of focus control and focus error measurement for production wafers that utilize the lens aberration of the exposure tool system. The authors call this method FMLA (focus monitoring using lens aberration). In general, astigmatism causes a difference in the optimum focal point between the horizontal and vertical patterns in the same image plane. If a focus error occurs, regardless of the reason, a critical dimension (CD) difference arises between the sparse horizontal and vertical lines. In addition, this CD difference decreases or increases monotonously with the defocus value. That is to say, it is possible to estimate the focus errors to measure the vertical and horizontal line CD formed by exposure tool with astigmatism. In this paper, the authors examined the FMLA technique using astigmatism. First, focus monitoring accuracy was investigated. Using normal scholar type simulation, FMLA was able to detect a 32.3-nm focus error when 10-mλ astigmatism was present. Furthermore, we verified that it was possible to experimentally detect a 20-nm focus error for gate layer of 90-nm logic devices. In tilt error evaluation, the estimated tilt error value was separated by 0.3-ppm from the input value into exposure tool parameters. Finally, when FMLA was applied to gate layer of 90-nm logic devices, inter lot distribution was decreased from 6.8-nm to 2.8-nm, and it was proved that FMLA using astigmatism was an effective method in device manufacturing.

Impact of lens aberration on pattern symmetry of DRAM cells

The impact of lens aberrations become more noticeable in the low k1 region, which is where a Krypton Fluoride (KrF) exposure tool exposes a pattern 0.18 micrometers . Lens aberrations affect pattern fidelity and line width uniformity across an exposure field. In particular, the isolation layer pattern of DRAM cells is very sensitive to lens aberrations. We focused on this pattern in our investigation of the impact of lens aberrations and found that asymmetric deformations were caused only by odd components expressed by Zernike polynomials. The magnitude of the impact changed by pattern condition, shape, image tonality, dimension, and term of Zernike polynomials. Using the Monte Carlo method, we simulated a permissible amount of lens aberrations that meet property requirements of a device. As a result, the odd components of lens aberrations were found to require less than 0.020 (lambda) in 0.18-micrometers generation and 0.015 (lambda) in 0.15-micrometers generation. Our rough estimate of the amount of lens aberrations on a KrF scanner was derived from the relationship between a practical printed image and simulated image.

Improvement of CD uniformity in 180 nm LSI manufacturing by optimizing illumination system

Line width control is a key factor in LSI manufacturing. This paper describes the relationship between line width uniformity and the illumination system of an exposure tool. Variation in the local value of partial coherence a is the cause of the optical proximity effect (OPE) variation across the image field of an exposure tool. By quantifying partial coherence /spl sigma/ and decreasing a variation, OPE variation within the image field was improved from 21.2 nm to 8.8 nm. We reduced OPE variation among tools by setting up these tools with agreeing a values. This paper also discusses the effect of illumination source uniformity on line width. Nonuniformity of an illumination source induces a line width difference between pair lines. We improved the treatment for these problems by adjusting the illumination source uniformity.

Novel optimization method for antireflection coating

Anti-reflection technology is necessary for controlling line widths. Minimization of the line width deviation in the gate layer is particularly important for improving yields and stabilizing device performance. We have developed a novel anti-reflection effect monitor (AREM) for the optimization of anti-reflection coating materials. Generally, the anti-reflection effect is quantified as the amplitude of the resist sensitivity curve against the resist thickness on an anti- reflection coated substrate. In AREM, a sample wafer is prepared with a gate structure and LOCOS step. Then anti-reflection material is deposited on the wafer and resist is subsequently coated on it. Here, the resist thickness changes gradually away from the step. Hundreds of isolated lines are patterned parallel to the LOCOS step at 0.1 micrometers intervals away from the step. Then each lines width is measured with an electrical probe and the curve of the line width versus the distance from the step is obtained, corresponding to the resist sensitivity curve against resist thickness. AREM is very accurate and can quantify the anti-reflection effect as a line width deviation.