Morio Inoue

Molybdenum‐Silicon Schottky Barrier

An ideal metal‐semiconductor Schottky barrier contact was made by chemically depositing thin films of molybdenum on n‐type silicon by the hydrogen reduction of molybdenum pentachloride at temperatures between 390°C and 500°C. Current‐voltage, capacity‐voltage, and photoelectric measurements were used to investigate the characteristics of molybdenum‐silicon diodes thus produced. The junction is shown to be very close to the ideal Schottky barrier with the barrier height measured with respect to the Fermi energy of 0.57±0.02 eV.

Thin Silicon Dioxide Using the Rapid Thermal Oxidation (RTO) Process for Trench Capacitors

La croissance et les caracteristiques electriques des couches minces de dioxyde de silicium par le processus doxydation thermique rapide sont etudiees dans le cas des condensateurs plans et en tranchees. La croissance suit le modele lineaire-parabolique. Energies dactivation des constantes de vitesse lineaire et parabolique. On obtient de bonnes caracteristiques electriques en augmentant la temperature doxydation de 1000 o a 1150 o C. Pour les condensateurs en tranchees oxydes a 1150 o C, la disruption electrique de loxyde a lieu principalement pour des champs de 10∼12 mV/cm, avec une densite de courant de fuite de 3×10 −11 A/cm 2 , et la densite des etats electroniques dinterface est 3×10 10 cm −2 eV −1 . Le processus doxydation thermique rapide semble une technique prometteuse de fabrication des capacites en tranchees

Infrared Radiation Annealing of Ion‐Implanted Polycrystalline Silicon Using a Graphite Heater

Ion‐implanted polycrystalline silicon layers were annealed using the radiation from a graphite heater. 0.4 μm thick polycrystalline silicon films implanted with 40 keV P+ ions to a dose of were annealed in vacuum at 1000° – 1200°C for 10 – 60 sec. A minimum sheet resistance of 9 Ω/ was obtained for a sample which was encapsulated with a 0.3 μm PSG film and annealed at 1200°C for 10 sec. TEM photographs show that the grain size of polycrystalline silicon grew up to around 1.0 μm in diam. The activation of the implanted phosphorus, the annealing of a damaged layer, and the increase of grain size leads to the reduction of sheet resistance of polycrystalline silicon and the increase of carrier mobility.

Crystal Growth and Orientation of Vacuum Deposited Films of CdTe

Thick films of CdTe were deposited on amorphous quartz plates at normal and oblique incidences in vacuum, and their oriented growth was studied by X-ray diffraction and by electronmicroscope observation. It was found that fibrous crystallites having the [111] growth axis inclined to the incident beam. Lamellae structure normal to the fiber axis was visualized on etching or cleaving. The crystallographic polarity along the [111] direction of thick CdTe films deposited on amorphous quartz as well as some other substances was determined from a measurement of the piezoelectric effect of the films; the substrate side of most films was the Cd(111) plane and the film surface side was the Te(111) plane. The photovoltaic effect of vacuum-deposited films was discussed in terms of the crystallographic characteristics such as the polarity and the cubic-hexagonal transition.

Deep p-type layer formation using Al+ implantation and diffusion into Si

Abstract The formation of aluminum-diffused deep layers using Al+ ion implantation into Si and low temperature annealing was investigated. The n-type Si (111) wafers were ion implanted with aluminum at 80 and 120 keV and doses in the range of 1 × 1013–5 × 1015 cm−2. Good electrical activation was obtained by heating the wafer at low temperatures, (550–650°C). Al diffusion was studied in the range of 900–1200°C. Impurity profiles and electrical activation of Al+ ion implanted and annealed layers were measured with secondary ion mass spectroscopy (SIMS) and sheet resistance profiling respectively. The carrier concentration was found to be the solid solubility limit of Al in Si. The diffusion coefficient at 1200°C was determined to be 1.5 × 10−11 cm2/s, which is about ten times larger than that of B (1.3 × 10−12 cm2/s). A deep diffused p-type layer of 10–35 μm thickness was formed by heating at 1200°C for 2–30 h. A combination of Al+ implantation and low temperature diffusion was found to be a superior process to the method of using B+ ions for forming deep p-type diffused layers, since they have reduced damage which is of considerable importance for VLSI fabrication.

Damage analysis and engineering for ion implantation in ULSI process

Abstract To evaluate damaged silicon crystals, as implanted or after annealing in ULSI process, transmission electron microscopy (TEM), thermal wave, and scanning Raman microscopy techniques provide complementary methods for the detection of crystal lattice imperfections. Depth profile analysis using anodic oxidation-HF etching techniques, have also been developed for damage characterization. A new technique by combination of the anodic oxidation-HF etching and an atomic force microscopy (AFM) techniques is very suitable for the observation of the structure and distribution of the secondary defects. By using these damage characterization methods, clear understanding and effective prevention of the critical damage during ion implantation hold great promise for ULSI manufacturing.

Post-Annealing Effect on the Reliability of Ultra-Thin Silicon Dioxide with Polysilicon Gate

Time dependent dielectric breakdown (TDDB) characteristics and TEM observation of ultra-thin silicon dioxide with the polysilicon gate after post-annealing and oxidation at 1000-1100 °C are discussed. The high temperature post-annealing decreases the TDDB characteristics of ultra-thin oxide with polysilicon gate. The charge to breakdown is reduced drastically with increasing the annealing temperature and annealing time. The dielectric breakdown reliability degradation of ultra-thin tunneling oxide by the post-annealing can be explained as the partial oxide thinning and electric field concentration due to the increase of roughness at the polysilicon gate/ultra-thin tunneling oxide interface. This increase of roughness is due to the grain growth of polysilicon gate and viscous flow of oxide, which are enhanced with increasing the annealing temperature and time.

Characterization of Ion Implantation Dose by Raman Scattering and Photothermal Wave Techniques

Damage in silicon crystals implanted with various doses at different acceleration energies has been characterized by Raman scattering and photothermal wave techniques. Depth profiles of the damage in the implanted silicon crystals have been estimated from the Raman scattering measurements. The Raman scattering and photothermal wave measurements were compared. The results show that the quantities measured by the two techniques are strongly correlated at low dose levels and that they can be used to characterize damage induced by ion implantation.