Moritz Mühlenthaler

Fairness in academic course timetabling

We consider the problem of creating fair course timetables in the setting of a university. The central idea is that undesirable arrangements in the course timetable, i.e., violations of soft constraints, should be distributed in a fair way among the stakeholders. We propose and discuss in detail two fair versions of the popular curriculum-based course timetabling (CB-CTT) problem, the MMF-CB-CTT problem and the JFI-CB-CTT problem, which are based on max–min fairness (MMF) and Jain’s fairness index (JFI), respectively. For solving the MMF-CB-CTT problem, we present and experimentally evaluate an optimization algorithm based on simulated annealing. We introduce three different energy difference measures and evaluate their impact on the overall algorithm performance. The proposed algorithm improves the fairness on 20 out of 32 standard instances compared to the known best timetables. The JFI-CB-CTT problem formulation focuses on the trade-off between fairness and the aggregated soft constraint violations. Here, our experimental evaluation shows that the known best solutions to 32 CB-CTT standard instances are quite fair with respect to JFI. Our experiments show that the fairness can often be improved at the cost of only a small increase in the overall amount of penalty.

Degree-Constrained Subgraph Reconfiguration is in P

The degree-constrained subgraph problem asks for a subgraph of a given graph such that the degree of each vertex is within some specified bounds. We study the following reconfiguration variant of this problem: Given two solutions to a degree-constrained subgraph instance, can we transform one solution into the other by adding and removing individual edges, such that each intermediate subgraph satisfies the degree constraints and contains at least a certain minimum number of edges? This problem is a generalization of the matching reconfiguration problem, which is known to be in P. We show that even in the more general setting the reconfiguration problem is in P.

An FPGA implementation of a threat-based strategy for Connect6

In this paper, we present a strategy and an FPGA implementation of a Connect6 player submitted to the FPT 2011 Design Competition. Connect6 is a two-player strategy board game. The winner of the game is the player who first gets six pieces of his color in a connected horizontal, vertical or diagonal line. We assign a strategic value to each potential move depending on the current board configuration. Our approach uses a minimal amount of situation dependent game logic in order to take full advantage of the available compute resources and parallelism. The FPGA implementation of this strategy always wins against the software opponent provided for the competition. Additionally, our implementation wins on average against different software AIs from [1], as long as no sophisticated game-tree search is performed by the software.

Heterogeneous constraint handling for particle swarm optimization

We propose a generic, hybrid constraint handling scheme for particle swarm optimization called Heterogeneous Constraint Handling. Inspired by the notion of social roles, we assign different constraint handling methods to the particles, one for each social role. In this paper, we investigate two social roles for particles, ‘self’ and ‘neighbor’. Due to the usual particle dynamics, a powerful mixture of the two corresponding constraint handling methods emerges. We evaluate this heterogeneous constraint handling approach with respect to the complete set of the CEC 2006 benchmark instances. Our results indicate that a such a heterogeneous combination of two constraint handling methods often leads to significantly better results than running each individual constraint handling method separately and returning the best solution obtained.

Runtime Analysis of a Discrete Particle Swarm Optimization Algorithm on Sorting and OneMax

We present the analysis of a discrete particle swarm optimization (PSO) algorithm that works on a significantly large class of discrete optimization problems. Assuming a black-box setting, we prove upper and lower bounds on the expected number of function evaluations required by the proposed algorithm to solve the sorting problem and the problem of maximizing the number of ones in a bitstring, i.e., the function OneMax. We show that depending on the probability of moving towards the attractor, the expected optimization time may be polynomial or exponential. The cornerstone of our analysis are Theta-bounds on the expected time it takes until the PSO returns to the attractor. We obtain these bounds by solving linear recurrence equations with constant and non-constant coefficients. We also introduce a useful indistinguishability property of states of a Markov chain in order to obtain lower bounds on the expected optimization time of our proposed PSO algorithm.

ReOrder: Runtime datapath generation for high-throughput multi-stream processing

Modern Programmable FPGA-based SoCs that tightly couple CPU and programmable logic enable the acceleration of stream processing in hardware on-demand by making use of the available high input and output throughputs and the reconfigurability both in software and hardware. In this paper, we present the concept and implementation of a hardware unit called ReOrder that serves as a converter for multiple parallel streams of data read from and written to an accelerator. Our technique and programmable design allows flexible data access and connects different stream processing accelerators independent of the host data layout. In order to achieve a high accelerator throughput, it is necessary to determine an optimized datapath according to the accelerators internal schedule of input and output data. We are concerned with an online setting, in which either the data layout (e.g., in the case of modern database systems) or the accelerator operational mode change dynamically. Therefore, an algorithm is required which can be used at “runtime” in order to maintain an optimized datapath configuration. We propose an efficient heuristic algorithm and corresponding FPGA design that is able to translate arbitrary (multi-source) data layouts of the connected host system to generate any specified data stream of the accelerator at runtime within ms.

Real-World Academic Course Timetabling

We present a case study on automating the creation of course timetables at the school of engineering of the Friedrich-Alexander Universitat Erlangen-Nurnberg (FAU). We will address the formal model and discuss its relation to the popular CB-CTT problem model used for benchmarking. Furthermore, we will discuss relevant issues that arise when creating course timetables in practice. In particular, we will report on the integration of the timetabling system in the organizational framework, feedback mechanisms, acceptance issues, and quality management.

The University Course Timetabling Problem

Despite its simplicity, the UCTP is a computationally tough problem. We will review solution approaches to the UCTP and related problems and investigate combinatorial properties of the UCTP search space. We focus on establishing conditions that guarantee the connectedness of all clash-free timetables with respect to the Kempe-exchange operation.