Josef Angermeier

No-break dynamic defragmentation of reconfigurable devices

We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules and with inhomogeneities found in commonly used FPGAs. Our method is based on dynamic relocation of module positions during runtime, with only very little reconfiguration overhead; the objective is to maximize the length of contiguous free space that is available for new modules. We describe a number of algorithmic aspects of good defragmentation, and present an optimization method based on tabu search. Experimental results indicate that we can improve the quality of module layout by roughly 50% over static layout. Among other benefits, this improvement avoids unnecessary rejection of modules.

A comparison of embedded reconfigurable video-processing architectures

Using field programmable gate arrays (FPGAs) as accelerators for image or video processing operations and algorithms has gained increasing attention over the last few years. One reason for that is FPGAs are able to exploit both temporal and spatial parallelism. In this paper two platforms for FPGA-based real-time image and video processing are presented and compared against each other. With both of these platforms it is possible to update the physical resources during run-time by exploiting the dynamic partial reconfiguration capabilities of Xilinx Virtex FPGAs. The analysis of both platforms with respect to their benefits and draw-backs has led to the concept of an optimal FPGA-based dynamically and partially reconfigurable platform for real-time video and image processing.

Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads

When using dynamically and partially reconfigurable FPGAs in embedded systems, the scheduler needs to fulfill area and time requirements for each task. While those demands are already well studied in literature, another characteristic peculiarity of reconfigurable systems has been rather neglected: the reconfiguration overhead. However, scheduling algorithms considering the exclusive access to the reconfiguration port can improve the latency of obtained schedules considerably. In this paper, we present new scheduling heuristics and a methodology to compare approaches which take into consideration the reconfiguration overheads with those which disregard them. Furthermore, our experimental results give insight into possible performance increases and present problem instances for which the reconfiguration latency is negligible.

Dynamic Defragmentation of Reconfigurable Devices

We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules and with inhomogeneities found in commonly used FPGAs. Our method is based on dynamic relocation of module positions during runtime, with only very little reconfiguration overhead; the objective is to maximize the length of contiguous free space that is available for new modules. We describe a number of algorithmic aspects of good defragmentation, and present an optimization method based on tabu search. Experimental results indicate that we can improve the quality of module layout by roughly 50% over the static layout. Among other benefits, this improvement avoids unnecessary rejections of modules.

Stress-Aware Module Placement on Reconfigurable Devices

A lot of research has been spent on improving the reliability and extending the lifetime of ASIC and SoC devices, but only little on improving the long-term reliability of dynamically reconfigurable systems. In order to increase the lifetime of a reconfigurable device, we propose a placement strategy to distribute the stress equally on the reconfigurable resources at runtime such that all have a similar level of degradation. Thereby, we present a new aging model which is applied to estimate the influence of aging effects on dynamically reconfigurable devices, and which can be evaluated at runtime, while providing quite accurate aging results. Furthermore, we present a new stress-aware placement algorithm that takes the degradation of the reconfigurable resources into account and can significantly extend the lifetime of reconfigurable devices.

Placing multimode streaming applications on dynamically partially reconfigurable architectures

By means of partial reconfiguration, parts of the hardware can be dynamically exchanged at runtime. This allows that streaming application running in differentmodes of the systems can share resources. In this paper, we discuss the architectural issues to design such reconfigurable systems. For being able to reduce reconfiguration time, this paper furthermore proposes a novel algorithm to aggregate several streaming applications into a single representation, called merge graph. The paper also proposes an algorithm to place streaming application at runtime which not only considers the placement and communication constraints, but also allows to place merge tasks. In a case study, we implement the proposed algorithm as runtime support on an FPGA-based system on chip. Furthermore, experiments show that reconfiguration time can be considerably reduced by applying our approach.

The Erlangen Slot Machine – A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens)

We introduce a hardware platform called Erlangen Slot Machine (ESM) that has been built in Erlangen within the project ReCoNodes for enabling interdisciplinary research on reconfigurable computing. For this dynamically reconfigurable computer, the cooperation partner in Braunschweig provides algorithmic solutions, in particular for the optimization of module placements and inter-module communication. Eine Hardware-Plattform mit Namen Erlangen Slot Machine (ESM) wird beschrieben, die im Projekt ReCoNodes in Erlangen entstanden ist. Sie soll dazu dienen, methodische Ansätze und Anwendungen anderer Projekte zu testen und interdisziplinär zugänglich zu machen. Der Kooperationspartner in Braunschweig liefert algorithmische Lösungen für diesen dynamisch rekonfigurierbaren Rechner, insbesondere zur Optimierung der Modulplatzierung und der Kommunikation zwischen Modulen.

Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures

By means of partial reconfiguration, parts of the hardware can be dynamically exchanged during operation what allows to adapt the system to changing requirements, and even enables the implementation of self-managing systems. This however requires sophisticated system architectures as well as proper algorithmic runtime support. In this paper, we present an algorithm for placing streaming applications at runtime. The approach considers the heterogeneity of common FPGAs, such as Block-RAMs, as well as the routing restrictions of on-chip streaming interconnections. To reduce reconfiguration time, we extend the data flow graphs by OR-nodes to describe differing parts of applications while keeping their similarities. This allows us to model systems which only reconfigure differing parts when switching between applications. The proposed algorithm is implemented as runtime support on an FPGA-based system-on-chip.

ReCoNodes—Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices

Placement and scheduling are recognized as the most important problems when exploiting the benefit of partially reconfigurable devices such as FPGAs. For example, dynamically loading and unloading modules onto an FPGA causes fragmentation, and—in turn—may decrease performance. To counteract this effect, we use methods from algorithmics and mathematical optimization to increase the performance and present algorithms for placing, scheduling, and defragmenting modules on FPGAs. Taking communication between modules into account, we further present strategies to minimize communication overhead. Finally, we consider scheduling module requests with time-varying resource demands.

Bitonic Sorting on Dynamically Reconfigurable Architectures

Sorting is one of the most investigated tasks computers are used for. Up to now, not much research has been put into increasing the flexibility and performance of sorting applications by applying emph{reconfigurable} computer systems. There are parallel sorting algorithms (emph{sorting circuits}) which are highly suitable for VLSI hardware realization and which outperform sequential sorting methods applied on traditional software processors by far. But usually they require a large area that increases %But usually they also have a high area requirement, increasing with the number of keys to be sorted. This drawback concerns ASIC and statically reconfigurable systems. In this paper, we present a way to adopt the well-known Bitonic sorting method to dynamically reconfigurable systems such that this drawback is overcome. We present a detailed description of the design and actual implementation, and we present experimental results of our approach to show its benefits in performance and the trade-offs of our approach.