Mostafa Emam

Experimental Investigation of RF Noise Performance Improvement in Graded-Channel MOSFETs

In this paper, measured RF noise performance of graded-channel metal-oxide-semiconductor (MOS) transistors (GCMOS - also named laterally asymmetric channel transistors) shows impressive reduction in minimum noise figure (NF min) as compared to classical MOSFET transistors (with the same gate length Lg = 0.5 mum). The reason is proven to be because of the higher noise correlation coefficient (C). GCMOS also shows lower sensitivity to extrinsic thermal noise as compared to classical MOSFET. Moreover, it is demonstrated that the use of 0.5- mum-gate-length GCMOS gives a competitive RF noise performance as compared to 0.25-mum-gate-length classical nMOS transistors.

Radio-Frequency Study of Dopant-Segregated n-Type SB-MOSFETs on Thin-Body SOI

We present a detailed direct current and radiofrequency study of fully depleted dopant-segregated Schottky barrier (SB) MOSFETs on thin-body Silicon-on-Insulator. On-wafer scattering-parameter measurements of n-type NiSi source/drain SB-MOSFETs provide an in-depth understanding of key device parameters (transconductances and capacitances) as a function of the implanted arsenic dose, i.e., different SB height. Devices with 80-nm-channel length show a high ON current of 1150 mA/mm and exhibit a unity-gain cutoff frequency of fT = 140 GHz.

High-frequency performance of dopant-segregated NiSi S/D SOI SB-MOSFETs

In this paper, we present fully-depleted Schottky barrier MOSFETs with dopant-segregated NiSi source and drain junctions. Schottky barrier MOSFETs with a channel length of 80nm show high on-currents of 900 µA/µm for n-type devices with As segregation and 427 µA/µm for p-type devices with B segregation, respectively. A detailed high-frequency characterization proves the high performance of the devices with cut-off frequencies fT of 117 GHz for n-type and 63 GHz for p-type Schottky barrier MOSFETs and clearly elucidates the effects of extrinsic and intrinsic device parameters as a function of gate length.

Partially Depleted SOI Versus Deep N-Well Protected Bulk-Si MOSFETs: A High-Temperature RF Study for Low-Voltage Low-Power Applications

The design options for low-voltage low-power (LVLP) applications are not limited to the circuit level, but it should start with the right choice of device technology and architecture. This paper presents a comparative study between a special structure of bulk MOSFET called the deep n-well protected device and the partially depleted silicon-on-insulator device. This paper shows the advantage of each device for different operation schemes while concentrating on the RF behavior for very low bias conditions. The study shows the lower limit for the bias conditions for the devices to correctly operate in RF. It also presents the effect of high temperature on the key figures of merit for dc and RF operations for high-performance and LVLP operation regimes.

High Temperature DC and RF Behavior of Partially Depleted SOI versus Deep n-Well Protected Bulk MOSFETs

The introduction of deep n-well protection for bulk MOS transistors can highly enhance their DC and RF performance. It also gives the advantage of having floating-body and body-tied structures in bulk MOSFETs while eliminating the disadvantages related to the shift in performance between these two structures. We demonstrate that the high temperature, DC and RF performance of n-well isolated bulk MOSFETs are really competitive compared to the state-of-the-art Partially Depleted SOI MOS technology.

Body-Biasing Control on Zero-Temperature-Coefficient in Partially Depleted SOI MOSFET

This work investigates the possibility to tune the zero-temperature-coefficient (ZTC) points in partially depleted (PD) SOI nMOSFET technology by controlling the body-source forward bias (VBS). Measured transconductance and drain current in the saturation region at temperatures between 25 and 200degC were observed for various body-source forward bias conditions. It is found that the variation of threshold voltage (VTH) with body bias has an influence on ZTC points. The measurement results show wide voltage-range of gate-voltage giving either the transconductance ZTC point (VGS,ZTC9m) or the drain-current ZTC point (VGS,ZTC1DS) opening important opportunities in RF circuits design for nigh temperature applications.

Analog, RF and nonlinear behaviors of submicron graded channel partially depleted SOI MOSFETs

The DC, analog and RF behaviors as well as the nonlinear characteristics are shown for the first time for submicron graded channel partially depleted SOI MOSFETs. Previously reported advantages of long graded channel devices are extended for downscaled submicron graded channel devices presented in this work. These advantages cover all aspects of operation, being DC, analog, RF and nonlinear performances, which are investigated in comparison with classical MOS devices. These results are confirmed through robust measurements and accurate characterization techniques supported by well established extraction methods, especially for RF and nonlinear regimes of operation.

High Temperature Antenna Switches in 130 nm SOI Technology

This paper presents the design and the behavior vs. temperature of RF antenna switches in a 130 nm SOI technology. The design is implemented using two types of transistors; floating body and body tied transistors. It is shown that the floating body transistor is the best candidate for the design of RF antenna switches implemented in a fully integrated RF communication system. Outstanding high temperature behavior is also emphasized on a temperature range from 25degC to

High temperature RF behavior of SOI MOSFET transistors for low power low voltage applications

This paper presents a new approach to optimize the RF performance at high temperatures for low power low voltage applications. It is shown that the correct choice of the bias point can result in an improvement of the RF behavior of SOI transistors with increasing the temperature, which is opposite to the traditional degradation of RF behavior with increasing temperature. This approach is confirmed by RF measurements for both floating-body and body-tied SOI MOSFET transistors.

Comparison between the behavior of submicron graded-channel SOI nMOSFETs with fully- and partially-depleted operations in a wide temperature range

In this work electrical properties of GC SOI nMOSFETs from two different technologies were presented for temperatures ranging between 90K and 380K. It has been shown that the increase of mobility with temperature reduction is larger than for devices with lighter dopind levels. Heavily doped GC from transistors shown constant threshold voltage over the entire temperature range, as it lies close to the ZTC point. Although the temperature lowering leads devices to operate in full depletion, GC devices with thin gate oxide presented GIFBE effect due to the leakage current reduction. The subthreshold swing of heavily doped GC transistors have shown to depart the theoretical limit for T higher than 250K, indicating a change in the operation mode from fully to partially-depleted.