Mostafa H. Abd-El-Barr

CMOS multiple-valued logic design. I. Circuit implementation

A CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed. The set consists of literal, cycle, complement of literal, complement of cycle, min, and tsum operators. In all of the circuits, multiple-valued logic levels are represented in terms of current values. Binary voltage signals are generated inside the circuits using a threshold circuit element. These binary voltage signals are used to generate control signals for switches to realize appropriate current levels for the desired multiple-valued logic levels. Transient analysis simulations (using HSPICE) to verify the functionality of the designed circuits and the effect of variation in process parameters are also reported. >

On the optimization of MOS circuits

Optimizing the number of transistors in a complex MOS gate, which is important for minimizing chip area and delay in VLSI designs, is an NP-complete problem. The worst-case computational complexity of graph-oriented algorithms used in existing approaches is exponential in the number of transistors. This problem is addressed through the use of bridging switches. A theory and an algorithm for optimization of MOS switch networks using an edge-merging technique are proposed. The worst-case computational complexity of the heuristic algorithm proposed is O(n/sup 5/e/sup 2/), where n is the number of nodes and e is the number of edges in the switch network. >

The incremental-cost approach for synthesis of CCD 4-valued unary functions

A novel approach to the synthesis of one-variable four-valued functions using CCDs (charge-coupled devices) is presented. Starting at zero cost, a search is conducted for the possible functions that can be realized using basic CCD gate structures. These functions are recorded in a list. At a given cost C, each of the four possibilities of using the addition, overflow, inhibit, and multiplication as an output gate is considered. For each possibility, the set of possible inputs to the gate are determined and used. Only those outputs which are not covered at lower costs are added to the list. The cost is then incremented by one and the search is repeated for new functions. The process terminates when all 256 possible functions are in the list. Using this approach, it is shown that in 195 functions (76% of the total) there is a cost improvement compared to existing approaches.<<ETX>>

CMOS multiple-valued logic design. II. Function realization

For pt. I see ibid vol. 40, no. 8 p 503-14 (1993). The performance of the set of operators proposed in pt. I is compared with existing sets of operators for the realization of multiple-valued logic (MVL) functions. In pt. I, a set of operators was proposed consisting of literal, cycle, complement of literal, complement of cycle, min, and tsum operators (Set 1). This set of operators is compared to two existing sets of operators consisting of literal, complement of literal, min, and tsum operators (Set 2) and literal, min, and tsum operators (Set 3). For 3-valued 2-variable MVL functions, it is shown that the maximum number of product terms (PTs) required to realize all functions can be reduced to three PTs (using the Set 1 operators) from five PTs (using the Set 2 operators) and six PTs (using the Set 3 operators). In addition, it is shown that the average number of PTs required to realize all the functions reduces to 2.61 (using the Set 1 operators) from 3.19 (using the Set 2 operators) and 3.61 (using the Set 3 operators). It is anticipated that similar improvements are possible for higher valued logic. Realizations of a 4-valued 2-variable function based on different sets of operators are included to support such a claim. >

On the synthesis of MVL functions for current-mode CMOS circuits implementation

Four-valued, one-variable multivalued logic (MVL) functions are synthesized using current-mode CMOS logic (CMCL) circuits. Use is made of the fact that in CMCL, addition of logic values (represented using discrete current values) can be performed at no cost and that negative logic values are readily available by reversing the direction of current flow. A synthesis procedure that is based on the cost-table approach is proposed. The procedure results in less expensive (in terms of the number of transistors needed) realizations than those achieved using existing techniques.<<ETX>>

Algorithmic synthesis of MVL functions for CCD implementation

Algorithms for synthesis of four-valued one- and two-variable functions for CCD (charge coupled device) implementation are proposed. One-variable synthesis is based on the observation that the cost of a realization of a function f(x) increases in the presence of breaks, or negative transitions, in the value of f as x increases. The function is decomposed to minimize the number of such transitions. Two-variable functions are synthesized as a sum of products of literals, taking advantage of literals that are easily implemented in CCD technology. It is concluded that the proposed algorithms perform better than those published previously. >

Incremental-cost approach for the synthesis of CCD 4-valued unary functions

Several approaches have been developed for the synthesis of one-variable 4-valued functions using CCDs. In all these approaches an attempt has been made to reduce the cost of implementing a given function. In this paper, we propose a new approach for the synthesis of such functions. Starting at zero cost, a search is conducted for the possible functions that can be realized using basic CCD gate structures. These functions are recorded in a list. At a given cost C, each of the four possibilities of using addition, overflow, inhibit, and multiplication as an output gate is considered. For each possibility, the set of possible inputs to the gate are determined and used. Only those outputs which are not covered at lower costs are added to the list. The cost is then incremented by one and the search is repeated for new functions. The process terminates when all possible 256 functions are in the list. Using this approach, it is shown that in 195 functions (76% of the total) there is a cost improvement compared ...

Graph-based output phase assignment for PLA minimization

A graph-based approach to finding near-optimal output phase assignments for PLA minimization is presented. A distinctive feature of the approach is that it exploits the necessary and sufficient conditions to reduce the number of product terms needed for PLA implementation and permits the use of existing graph algorithms to solve the PLA output phase optimization problem. The work is based on the transformation of a PLA into a graph whose vertices are the set of conditions required to reduce each product term of the PLA, and whose edges represent the relations between these conditions. Cliques (completely connected subgraphs) in the graph correspond to the output phase assignments required to reduce the product terms represented by the vertices in the cliques. The optimal PLA output phase assignment problem is then formulated as the well-studied problem in graph theory: finding maximum cliques in graphs. Using an existing algorithm for locating cliques in graphs, a modified greedy algorithm is proposed to compute output phase assignments for logic functions in polynomial time. Experimental results using a number of benchmark functions show that the graph-based approach can achieve optimal or near-optimal output phase assignment for PLA minimization and can lead to PLAs with fewer product terms than achieved using existing approaches. >

On multiple-valued logic design of neural networks

Neural networks are massively parallel systems having a large number of neurodes, an electronic approximation of a human neuron, with numerous interconnections between them. Using multiple-valued signaling it is possible to reduce interconnection complexity compared to the use of binary signals. This paper concentrates on multiple-valued logic (MVL) realization of neural networks in a current mode CMOS technology. Basic circuit elements used to realize MVL neural networks are also given.<<ETX>>

Use of simulated annealing to reduce 2-bit decoder PLAs

A 2-bit decoder programmable logic array (PLA) is an array of transistors that realizes the sum of products (realized by rows of transistors) of inputs taken from the outputs of 2-input 4-output decoders. Functions of several variables, which are assigned to the decoder inputs using Tomczuk and Millers heuristic algorithm to pair closely related variables using the autocorrelation of the functions, are realized using reduced area PLAs. The number of product rows (representing product terms) used in such PLAs, which is a function of the assignment of pairs of variables to the decoders, is reduced using simulated annealing techniques which are applied to permuting the assignment of input variables to the decoder inputs.