R.J. Bolton

CMOS multiple-valued logic design. I. Circuit implementation

A CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed. The set consists of literal, cycle, complement of literal, complement of cycle, min, and tsum operators. In all of the circuits, multiple-valued logic levels are represented in terms of current values. Binary voltage signals are generated inside the circuits using a threshold circuit element. These binary voltage signals are used to generate control signals for switches to realize appropriate current levels for the desired multiple-valued logic levels. Transient analysis simulations (using HSPICE) to verify the functionality of the designed circuits and the effect of variation in process parameters are also reported. >

A segmented matched filter for CDMA code synchronization in systems with Doppler frequency offset

This paper presents a segmented matched filter (SMF) for codephase acquisition in direct sequence spread spectrum systems. While conventional matched filters provide fast acquisition in the presence of high co-user noise, they are unable to handle significant carrier frequency offset (Doppler). This problem is alleviated by segmentation with non-coherent summation. The paper develops expressions to approximately relate the matched filter partitioning to the pre-detection filter and dwell time integrator of the conventional non-coherent correlator. It also investigates 1-bit versus 2-bit quantization. A mixed-signal application specific integrated circuit (ASIC) has been fabricated to implement a 512 chip SMF with half chip codephase resolution. The paper presents calculated and measured probability density functions (pdf) for the filter output decision variable for 10, 25, and 50 co-users with 0 to 20 kHz Doppler shift. For the example of a GPS receiver, expected acquisition time is shown as a function of multiple access interference and carrier Doppler shift.

A self-restored current-mode CMOS multiple-valued logic design architecture

This paper discusses a self-restored architecture for current-mode CMOS multiple-valued logic (MVL) design. The self-restored architecture is characterized by using both current-mode MVL circuits and voltage-mode binary circuits to implement MVL functions and to restore output signals simultaneously. Binary gates are used within the design architecture so that MVL-binary or binary-MVL conversion circuits are not required to interface with binary circuits. The average size of the resulting circuits is smaller than those using standard MVL operators.

CMOS multiple-valued logic design. II. Function realization

For pt. I see ibid vol. 40, no. 8 p 503-14 (1993). The performance of the set of operators proposed in pt. I is compared with existing sets of operators for the realization of multiple-valued logic (MVL) functions. In pt. I, a set of operators was proposed consisting of literal, cycle, complement of literal, complement of cycle, min, and tsum operators (Set 1). This set of operators is compared to two existing sets of operators consisting of literal, complement of literal, min, and tsum operators (Set 2) and literal, min, and tsum operators (Set 3). For 3-valued 2-variable MVL functions, it is shown that the maximum number of product terms (PTs) required to realize all functions can be reduced to three PTs (using the Set 1 operators) from five PTs (using the Set 2 operators) and six PTs (using the Set 3 operators). In addition, it is shown that the average number of PTs required to realize all the functions reduces to 2.61 (using the Set 1 operators) from 3.19 (using the Set 2 operators) and 3.61 (using the Set 3 operators). It is anticipated that similar improvements are possible for higher valued logic. Realizations of a 4-valued 2-variable function based on different sets of operators are included to support such a claim. >

A low latency architecture for computing multiplicative inverses and divisions in GF(2/sup m/)

A low latency architecture to compute the multiplicative inverse and division in a finite field GF(2/sup m/) is presented. Compared to other proposals with the same complexity, this circuit has a lower latency and can be used in error-correction or cryptography to increase the system throughput. This architecture takes advantage of the simplicity to compute powers (2/sup i/) of an element in a Galois field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit.

Computer-aided design of recursive digital filters with coefficients having restricted minimal representation

A strategy for computer-aided design of recursive digital filters with canonical signed digit (CSD) coded coefficients is presented. The algorithm allows restriction of the number of add/subtract operations the coefficients imply as multipliers. Several examples are given which demonstrate that the design method yields efficient filters with acceptable responses.

Dynamic silicon firewall

Firewalls filter information as it flows through a network. This filter can be implemented in hardware or software and can be used to protect computers from unwanted access. While software firewalls are considered easier to set up and use, hardware firewalls are often considered faster and more secure. Absent from the marketplace is an embedded hardware solution applicable to desktop systems. Traditional software firewalls use the CPU of the computer to filter packets; this is disadvantageous because the computer can become unusable during a network attack when the CPU is swamped by the firewall process. Traditional hardware firewalls are usually implemented in a single location, between a private network and the Internet. Depending on the size of the private network, a hardware firewall may be responsible for filtering the network traffic of hundreds of clients. This not only makes the required hardware firewall quite expensive, but dedicates those financial resources to a single point that may fail. The dynamic silicon firewall project implements a hardware firewall using a soft-core processor with a custom peripheral designed using a hardware description language. Embedding this hardware firewall on each network interface card in a network would offer many benefits. It would avoid the aforementioned denial of service problem that software firewalls are susceptible to since the custom peripheral handles the filtering of packets. It could also reduce the complexity required to secure a large private network, and eliminate the problem of a single point of failure. Also, the dynamic silicon firewall requires little to no administration since the filtering rules change with the users network activity. The design of the dynamic silicon firewall incorporates the best features from traditional hardware and software firewalls, while minimizing or avoiding the negative aspects of both

A VHDL library for current-mode CMOS multiple-valued logic

This paper discusses the design and use of a VHDL library for current-mode CMOS multiple-valued logic (MVL) simulation. The library has basic MVL entities, complex MVL entities as well as standard binary logic gates. A bus resolution function working cooperatively with the basic MVL entities allows MVL logic levels (currents) in individual connections to be output. Design examples of a quaternary full adder and one segment of a match filter are presented along with both VHDL and circuit simulation results.

FPGA based reconfigurable body area network using Nios II and uClinux

This paper presents a reconfigurable Body Area Network (BAN) system that can be used to monitor human vital signs and identify abnormalities. The identification of clinically significant patterns in electrocardiogram (ECG) data is the application used to verify the system operation as well as to demonstrate reconfigurability of the system. Data files from the MIT-BIH Arrhythmia database were used for this purpose. As built, the system demonstrates the ability to record raw ECG data and detect and record R-R intervals as well as premature ventricular contractions. Moreover, the overall system was designed to be highly reconfigurable, allowing it to be used for other BAN applications besides pattern recognition in ECG data signals.

On multiple-valued logic design of neural networks

Neural networks are massively parallel systems having a large number of neurodes, an electronic approximation of a human neuron, with numerous interconnections between them. Using multiple-valued signaling it is possible to reduce interconnection complexity compared to the use of binary signals. This paper concentrates on multiple-valued logic (MVL) realization of neural networks in a current mode CMOS technology. Basic circuit elements used to realize MVL neural networks are also given.<<ETX>>