Mostafa Rahimi Azghadi

A novel design for quantum-dot cellular automata cells and full adders

Quantum-dot Cellular Automata (QCA) is a novel and potentially attractive technology for implementing computing architectures at the nano-scale. The basic Boolean primitive in QCA is the majority gate. In this study we present a novel design for QCA cells and another possible and unconventional scheme for majority gates. By applying these items, the hardware requirements for a QCA design can be reduced and circuits can be simpler in level and gate counts. As an example, a one bit QCA adder is constructed by applying our new scheme. Beside, we prove that how our reduction method decreases gate counts and levels in comparison to the other previous methods.

Spike-Based Synaptic Plasticity in Silicon: Design, Implementation, Application, and Challenges

The ability to carry out signal processing, classification, recognition, and computation in artificial spiking neural networks (SNNs) is mediated by their synapses. In particular, through activity-dependent alteration of their efficacies, synapses play a fundamental role in learning. The mathematical prescriptions under which synapses modify their weights are termed synaptic plasticity rules. These learning rules can be based on abstract computational neuroscience models or on detailed biophysical ones. As these rules are being proposed and developed by experimental and computational neuroscientists, engineers strive to design and implement them in silicon and en masse in order to employ them in complex real-world applications. In this paper, we describe analog very large-scale integration (VLSI) circuit implementations of multiple synaptic plasticity rules, ranging from phenomenological ones (e.g., based on spike timing, mean firing rates, or both) to biophysically realistic ones (e.g., calcium-dependent models). We discuss the application domains, weaknesses, and strengths of various representative approaches proposed in the literature, and provide insight into the challenges that engineers face when designing and implementing synaptic plasticity rules in VLSI technology for utilizing them in real-world applications.

A novel QCA multiplexer design

Quantum-dot Cellular Automata is a novel nanotechnology that promises extra low-power, extremely dense and high speed structure for construction of logical circuits at a nano-scale. Moreover, multiplexer is a useful component for the design of many important circuits. This paper proposes a novel and efficient design of 2:1 multiplexer in the QCA. The proposed multiplexer has been compared to few recent designs in terms of area, speed and complexity. Comparison of results illustrates significant improvements in our design as compared to traditional approaches. Also, simulation proves that the proposed multiplexer design is completely robust and more sustainable to high input frequency, as compared to other designs. Simulations have been carried out using the QCA Designer, a layout and simulation tool for QCA.

Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design

Full-adders are the core element of the complex arithmetic circuits like addition, multiplication, division and exponentiation. Regarding to this importance, new idea and investigations for constructing full-adders are required. As far as related literature is concerned, generality and ease of use, as well as voltage and transistor scaling are considerable advantages of CMOS logic design versus other design style such as CPL specially when cell-based design are targeted. This paper proposes a novel, symmetric and efficient design for a CMOS 1-bit full-adder. Besides, another fully symmetric full-adder has been presented. Results and simulations demonstrate that the proposed design leads to an efficient full-adder in terms of power consumption, delay and area in comparison to a well-known conventional full-adder design. The post-layout simulations have been done by HSPICE with nanometer scale transistors considering all parasitic capacitors and resistors.

Novel VLSI implementation for triplet-based spike-timing dependent plasticity

Spike Timing-Dependent Plasticity (STDP) is one of several plasticity rules that is believed to play an important role in learning and memory in the brain. In conventional pair-based STDP learning, synaptic weights are altered by utilizing the temporal difference between pairs of pre- and post-synaptic spikes. This learning rule, however, fails to reproduce reported experimental measurements when using stimuli either by patterns consisting of triplet or quadruplet of spikes or increasing the repetition frequency of pairs of spikes. Significantly, a previously described spike triplet-based STDP rule succeeds in reproducing all of these experimental observations. In this paper, we present a new spike triplet-based VLSI implementation, that is based on a previous pair-based STDP circuit [1]. This implementation can reproduce similar results to those observed in various physiological STDP experiments, in contrast to traditional pair-based VLSI implementation. Simulation results using standard 0.35 µm CMOS process of the new circuit are presented and compared to published experimental data [2].

Population-Based Optimization Algorithms for Solving the Travelling Salesman Problem

[Extract] Population based optimization algorithms are the techniques which are in the set of the nature based optimization algorithms. The creatures and natural systems which are working and developing in nature are one of the interesting and valuable sources of inspiration for designing and inventing new systems and algorithms in different fields of science and technology. Evolutionary Computation (Eiben& Smith, 2003), Neural Networks (Haykin, 99), Time Adaptive Self-Organizing Maps (Shah-Hosseini, 2006), Ant Systems (Dorigo & Stutzle, 2004), Particle Swarm Optimization (Eberhart & Kennedy, 1995), Simulated Annealing (Kirkpatrik, 1984), Bee Colony Optimization (Teodorovic et al., 2006) and DNA Computing (Adleman, 1994) are among the problem solving techniques inspired from observing nature. In this chapter population based optimization algorithms have been introduced. Some of these algorithms were mentioned above. Other algorithms are Intelligent Water Drops (IWD) algorithm (Shah-Hosseini, 2007), Artificial Immune Systems (AIS) (Dasgupta, 1999) and Electromagnetism-like Mechanisms (EM) (Birbil & Fang, 2003). In this chapter, every section briefly introduces one of these population based optimization algorithms and applies them for solving the TSP. Also, we try to note the important points of each algorithm and every point we contribute to these algorithms has been stated. Section nine shows experimental results based on the algorithms introduced in previous sections which are implemented to solve different problems of the TSP using well-known datasets.

Tunable low energy, compact and high performance neuromorphic circuit for spike-based synaptic plasticity

Cortical circuits in the brain have long been recognised for their information processing capabilities and have been studied both experimentally and theoretically via spiking neural networks. Neuromorphic engineers are primarily concerned with translating the computational capabilities of biological cortical circuits, using the Spiking Neural Network (SNN) paradigm, into in silico applications that can mimic the behaviour and capabilities of real biological circuits/systems. These capabilities include low power consumption, compactness, and relevant dynamics. In this paper, we propose a new accelerated-time circuit that has several advantages over its previous neuromorphic counterparts in terms of compactness, power consumption, and capability to mimic the outcomes of biological experiments. The presented circuit simulation results demonstrate that, in comparing the new circuit to previous published synaptic plasticity circuits, reduced silicon area and lower energy consumption for processing each spike is achieved. In addition, it can be tuned in order to closely mimic the outcomes of various spike timing- and rate-based synaptic plasticity experiments. The proposed circuit is also investigated and compared to other designs in terms of tolerance to mismatch and process variation. Monte Carlo simulation results show that the proposed design is much more stable than its previous counterparts in terms of vulnerability to transistor mismatch, which is a significant challenge in analog neuromorphic design. All these features make the proposed design an ideal circuit for use in large scale SNNs, which aim at implementing neuromorphic systems with an inherent capability that can adapt to a continuously changing environment, thus leading to systems with significant learning and computational abilities.

Efficient design of triplet based Spike-Timing Dependent Plasticity

Spike-Timing Dependent Plasticity (STDP) is believed to play an important role in learning and the formation of computational function in the brain. The classical model of STDP which considers the timing between pairs of pre-synaptic and post-synaptic spikes (p-STDP) is incapable of reproducing synaptic weight changes similar to those seen in biological experiments which investigate the effect of either higher order spike trains (e.g. triplet and quadruplet of spikes) [1]-[3], or, simultaneous effect of the rate and timing of spike pairs [4] on synaptic plasticity. In this paper, we firstly investigate synaptic weight changes using a p-STDP circuit [5] and show how it fails to reproduce the mentioned complex biological experiments. We then present a new STDP VLSI circuit which acts based on the timing among triplets of spikes (t-STDP) that is able to reproduce all the mentioned experimental results. We believe that our new STDP VLSI circuit improves upon previous circuits, whose learning capacity exceeds current designs due to its capability of mimicking the outcomes of biological experiments more closely; thus plays a significant role in future VLSI implementation of neuromorphic systems.

A Hybrid CMOS-Memristor Neuromorphic Synapse

Although data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper proposes a high-performance nano-scale Complementary Metal Oxide Semiconductor (CMOS)-memristive circuit, which mimics a number of essential learning properties of biological synapses. The proposed synaptic circuit that is composed of memristors and CMOS transistors, alters its memristance in response to timing differences among its pre- and post-synaptic action potentials, giving rise to a family of Spike Timing Dependent Plasticity (STDP). The presented design advances preceding memristive synapse designs with regards to the ability to replicate essential behaviours characterised in a number of electrophysiological experiments performed in the animal brain, which involve higher order spike interactions. Furthermore, the proposed hybrid device CMOS area is estimated as

Programmable neuromorphic circuits for spike-based neural dynamics

600\ \mu {\text{m}}^2