Moti Medina

Property Testing of Planarity in the CONGEST model

We give a distributed algorithm in the sf CONGEST model for property testing of planarity with one-sided error in general (unbounded-degree) graphs. Following Censor-Hillel et al. (DISC 2016), who recently initiated the study of property testing in the distributed setting, our algorithm gives the following guarantee: For a graph G = (V,E) and a distance parameter ε, if G is planar, then every node outputs sf accept, and if G is ε-far from being planar (i.e., more than εcdot |E| edges need to be removed in order to make G planar), then with probability 1-1/rm poly (n) at least one node outputs sf reject. The algorithm runs in O(log|V|cdotpoly(1/ε)) rounds, and we show that this result is tight in terms of the dependence on |V|. Our algorithm combines several techniques of graph partitioning and local verification of planar embeddings. Furthermore, we show how a main subroutine in our algorithm can be applied to derive additional results for property testing of cycle-freeness and bipartiteness, as well as the construction of spanners, in minor-free (unweighted) graphs.

Online Generalized Caching with Varying Weights and Costs

We present a new extension of the generalized caching/paging problem that allows the adversary to arbitrarily change the cost or weight of the currently requested page. We present modifications of previous algorithms for generalized caching to handle varying page weights and page costs. In particular, a deterministic algorithm based on~citeYoung02,CaoIrani97 for an

On-Line Path Computation and Function Placement in SDNs

(h,k)

10*: The Digital Abstraction

-competitive algorithm with competitive ratio

Near-optimal metastability-containing sorting networks

k/(k-h+1)

Faster and Simpler Distributed Algorithms for Testing and Correcting Graph Properties in the CONGEST-Model.

is presented. In addition, a randomized algorithm based on~citeBansalBN12,AdamaszekCER12 with competitive ratio

Digital Logic Design: Preface

O(łog k)

Digital Logic Design: Bibliography

is presented. We present three applications that can be supported via reductions to generalized caching with varying page weights and page costs. These applications are: (1)~support of subsets of pages that must be simultaneously present in the cache before entry to a critical section (i.e., working sets), (2)~change of page size due to compression and decompression, (3)~variable cache size (i.e., elastic caches).

Digital Logic Design: Signed Addition

We consider service requests that arrive in an online fashion in Software-Defined Networks (SDNs) with network function virtualization (NFV). Each request is a flow with a high-level specification of routing and processing (by network functions) requirements. Each network function can be performed by a specified subset of servers in the system. The algorithm needs to decide whether to reject the request, or accept it and with a specific routing and processing assignment, under given capacity constraints (solving the path computation and function placement problems). Each served request is assumed to “pay” a pre-specified benefit and the goal is to maximize the total benefit accrued. In this paper we first formalize the problem, and propose a new service model that allows us to cope with requests with unknown duration without preemption. The new service model augments the traditional accept/reject schemes with a new possible response of “stand by.” We also present a new expressive model to describe requests abstractly using a “plan” represented by a directed graph. Our algorithmic result is an online algorithm for path computation and function placement that guarantees, in each time step, throughput of at least a logarithmic fraction of a (very permissive) upper bound on the maximal possible benefit.

Digital Logic Design: Propositional Logic

The term a digital circuit refers to a device that works in a binary world. In the binary world, the only values are zeros and ones. In other words, the inputs of a digital circuit are zeros and ones, and the outputs of a digital circuit are zeros and ones. Digital circuits are usually implemented by electronic devices and operate in the real world. In the real world, there are no zeros and ones; instead, what matters is the voltages of inputs and outputs. Since voltages refer to energy, they are continuous (unless quantum physics is used). So we have a gap between the continuous real world and the two-valued binary world. One should not regard this gap as absurd. Digital circuits are only an abstraction of electronic devices. In this chapter, we explain this abstraction, called the digital abstraction . In the digital abstraction, one interprets voltage values as binary values. The advantages of the digital model cannot be overstated; this model enables one to focus on the digital behavior of a circuit, to ignore analog and transient phenomena, and to easily build larger, more complex circuits out of small circuits. The digital model together with a simple set of rules, called design rules , enable logic designers to design complex digital circuits consisting of millions of gates that operate as expected. TRANSISTORS The basic building blocks of digital electronic circuits are transistors . The hierarchy starts with transistors, from which gates are built.