Motoki Kobayashi

High Temperature Performance of 3C-SiC MOSFETs with High Channel Mobility

Transistor performances of lateral and vertical 3C-SiC MOSFETs are investigated in the temperature range of 25 °C to 300 °C. Both types of MOSFETs operate up to 300 °C and the lateral MOSFETs possess peak channel mobility of more than 100 cm2/(Vs) even at 300 °C for the [110]- and [-110]-channel directions. In both MOSFETs, on-currents decrease monotonically and threshold voltages shift negatively as the temperature increases. The temperature dependence of on-currents in the lateral MOSFETs is weaker than that in the vertical MOSFETs. The leakage current at the negative gate voltage increases at above 200 °C. The activation energies calculated from the leakage currents at 200 °C and 300 °C are about half of the 3C-SiC bandgap energy of 2.3 eV.

3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

High Quality 3C-SiC Substrate for MOSFET Fabrication

Quantitative efficacies of several methods for stacking fault (SF) reduction are evaluated using Monte Carlo (MC) simulation. SF density on a 3C–SiC {001} surface depends on interactions of adjoining SFs: annihilation between counter pairs of SFs and termination by orthogonal SF pairs. However, SFs are not entirely eliminated when growth occurs on undulant-Si and switch back epitaxy (SBE) due to spontaneous SF collimation that suppresses the annihilation probability of counter SFs. The MC simulation also reveals the efficacy of SF reduction method which includes the growth of 3C–SiC on finite area bounded by side walls. One can theoretically reduce the SF density below 100 cm-1 on 3C–SiC {001} surface. A practical way for eliminating the SF by termination at side walls is demonstrated, and it clearly exhibits that the SF density can be reduced under 120 cm-1.

Correlation between Leakage Current and Stacking Fault Density of p-n Diodes Fabricated on 3C-SiC

The correlation between leakage current and stacking fault (SF) density in p-n diodes fabricated on 3C-SiC homo-epitaxial layer is investigated. The leakage current density at reverse bias strongly depends on the SF density; an increase of one order of magnitude in the SF density enhances the leakage current by five orders of magnitude at a reverse bias of 400 V. In order to obtain commercially suitable MOSFETs with 10-4Acm-2 at 600V, the SF density has to be reduced below 6×104 cm-2. Photoemission caused by hot electrons, which travel along a leakage path, can be observed at the crossing between a SF and the edge of p-well region; where the maximum electric field is induced. The mechanism of the leakage current is discussed in detail in a separate paper.

Iron-Related Defect Centers in 3C-SiC

p-type 3C-SiC samples were implanted by iron (Fe) and investigated by means of deep level transient spectroscopy (DLTS). Corresponding argon (Ar) profiles with similar implantation damage were implanted in order to distinguish between iron-related defects and defects caused by implantation damage. Two donor-like iron-related centers were identified in p-type 3C-SiC.

Thermally-Assisted Tunneling Model for 3C-SiC p+-n Diodes

The dependence of the reverse current of 3C-SiC p+-n diodes on the temperature and on the reverse bias is measured and a model based on thermally-assisted tunneling is proposed to explain the dominating mechanism responsible for the leakage current. Taking into account an additional ohmic shunt resistance, the experimental reverse characteristics and thermal barrier heights B can sufficiently be reproduced.

Temperature-Dependence of the Leakage Current of 3C-SiC p+-n Diodes Caused by Extended Defects

A large leakage current (IR) is observed at reverse bias (VR) in 3C-SiC p+-n diodes. This leakage current is caused by a high density of stacking faults (SFs). The temperature dependence of IR is studied in the temperature range from 100 K to 295 K. It turns out that IR is thermally activated for reverse voltages VR  |170| V. We propose that within this voltage range IR originates from thermally assisted tunneling of electrons and holes from band-like states of the SFs into the conduction and valence band. For VR > |170| V, the thermal barrier is strongly reduced and direct tunneling dominates. These dependences are simulated in the framework of a simplified model.