Mouna Ben Said

Virtual prototyping of multiprocessor architectures using the open virtual platform

The complexity of System on Chip (SoC) design is increasing continuously with the use of MultiProcessor System on Chip (MPSoC) architectures. Mastering the complexity of these systems with a typical co-design workflow is really recommended. As such, computer aided design tools are needed to alleviate the task of designers. There is a lack of co-design tools that support multiprocessor architectures with Operating System (OS) support. Virtual platforms enable us to discover the interactive design space exploration at early stage in the design. They make designing embedded systems less tedious and elevate the low technical details to manage systems complexity and reduce time to market. In this paper, we present an exploration of the Open Virtual Platform (OVP) capabilities for multiprocessor architectures simulation. We particularly focus on the inter-processor communication facilities. We illustrate this study by a set of homogeneous and heterogeneous multiprocessor architectures with different memory hierarchies and peripherals followed by a run of several applications. We also integrate the use of OS to permit workload distribution among processors using several case studies to validate our system.

A timing constraints control technique for embedded real time systems

The real-time applications have a growing complexity and size which have to be well controlled. They can be viewed as a set of synchronized tasks, communicating and sharing critical resources. One of the main difficulties in the real-time application design is time constraints meeting. All tasks have to be running before their predefined deadlines. At this level, the integration of real time operating systems (RTOS) in the real-time systems design flow is necessary to enable scheduling tasks and managing the competition between them with respect of timing constraints. One of the problems encountered here is that one task may have different execution times. It may exceed its predefined WCET and then its deadline for many reasons. The problem is that one deadline exceeding may cause subsequent constraints violations which may disrupt the functioning of the system. This paper deals with this particular issue. It presents a new technique that permits the monitoring of tasks under execution. It controls their timing constraints by means of watchdog concept and detects deadline missing. That information is used to tune the target application parameters in order to satisfy timing constraints for the further computation iterations. We have implemented this technique in the RTOS MicroC/OS-II using the EDF scheduling policy. This technique has been validated using an Altera FPGA prototyping platform and the 3D rendering application.

OS service update for an online adaptive embedded multimedia system

The increasing popularity of nomad multimedia systems put new challenges for their design: increasing functionalities, limited energy and computation resources. These systems must provide a maximum application quality of service (QoS) in the presence of a dynamically varying environment (e.g. video streaming and multimedia conferencing) and multiple resources constraints. To respond to the changing resource availability and application demands, a new class of adaptation method is emerged. It combines the adaptation simultaneously upon the dirrerent layers related to the target system: hardware, application and OS. This paper presents an overview of a multilayer. The global manager (GM) is uses to handle large and long-term variations whereas the local manager (LM) is used to guarantee the real time constraint. This paper focuses on the LM that intervenes only in the application layer and OS layer.

Design Pattern for self-adaptive RTE systems monitoring

Approaches for the development of self-adaptive real-time embedded (RTE) systems are numerous. However, there is still a lack of generic and reusable design which fits different systems and alleviate the designer task. Design patterns represent a promising solution to get fast and reusable design. Unfortunately, patterns dealing with self-adaptive RTE systems development are still not well tackled in the literature. The general structure of self-adaptive RTE systems is based on a MAPE loop which is composed of four basic adaptation processes: Monitor, Analyze, Plan, and Execute. In this paper, we define patterns for the monitoring and analyzing processes through the generalization of relevant existing adaptation approaches to improve their accessibility to new adaptive systems developers. To evaluate the work, the proposed patterns are applied to a relevant existing cross-layer adaptation framework.

Model-Based Design of Real Time Embedded Application Reconfiguration

Maximizing the system output quality under resource constraints presents an inherent challenge in the design of RTES. To deal with this issue, scaling the application quality level through algorithmic or parameters tuning is an interesting adaptation mechanism since it permits to handle the complexity of modern embedded applications. Unfortunately, this adaptation mechanism is still under-explored by existing model-based design approaches. It is also not supported by the UML MARTE profile. Therefore, we propose in this chapter a model-based design of application reconfiguration using the MARTE standard. We define an additional package extending the Software Resource Modeling sub-profile. Then, in order to promote reusability of our proposed extension and facilitate its use by non-experts, we exploited it in the definition of a design pattern for an adaptation RTES decision making process.

A Model Driven Approach for the Development of Fine-Grain Self-Adaptive Multitask and Networked RTE Systems

Scaling the applications output quality in order to meet constraints and keep preserving NFPs is an important adaptation technique in modern embedded systems. In this paper, we propose a model driven framework for the modeling, NFPs verification and application reconfiguration of multitask networked RTE systems. We use the UML standard and an extension of the MARTE profile for the system high level specification. Then we profit from the MDE capabilities to map system models to a verification and reconfiguration platform. We illustrate the effectiveness of our approach using a RTE system running CPU and network bandwidth intensive multimedia applications.