Yessine Hadj Kacem

A MARTE Extension for Global Scheduling Analysis of Multiprocessor Systems

Real-Time Systems are subject to Soft/Hard temporal constraints. Besides, a tasks scheduling step is required to meet the maximum of deadlines, for which there are different scheduling algorithms to do. However, nowadays real-time systems represent a serious issue for the worldwide industry due to their growing complexity. Indeed, since they are more susceptible to failures and deficiencies of development, it is crucial to rely on high level development methods. In this context, some researchers have proposed scheduling analysis within the new profile Modeling and Analysis of Real-Time and Embedded systems (MARTE), which supports both monoprocessor and multiprocessor scheduling algorithms. While supported multiprocessor scheduling algorithms are part of the partitioned approach, global approach algorithms have not been backed by MARTE yet. In the present paper, we seek to improve the meta-models of MARTE stereotypes to establish scheduling analysis for the global approach.

Using MDE and priority time petri nets for the schedulability analysis of embedded systems modeled by UML activity diagrams

This paper proposes a model driven approach for the schedulability analysis at an early stage of the embedded system development life-cycle. The activity diagram of Unified Modeling Language (UML) annotated with the profile for the Modeling and Analysis of Real-Time and Embedded systems (MARTE) is mapped into Priority Time Petri Net (PTPN) to enhance formal schedulability test of given real time tasks. The generated PTPN model is interpreted and executed to check whether a schedule of a task execution meets the imposed timing constraints. Therefore, the present paper focuses on the definition of temporal properties and tasks dependency by means of activity diagram and MARTE profile. Besides, it describes the transformation rules from analysis model to formal model.

Compositional specification of real time embedded systems by priority time Petri Nets

An important key challenge in Embedded Real Time Systems (ERTS) analysis is to provide a seamless scheduling strategy. Formal methods for checking the temporal characteristics and timing constraints at a high abstraction level have proven to be useful for making the development process reliable. In this paper, we present a Petri Net modeling formalism and an analysis technique which supports not only systems scheduling analysis but also the compositional specification of real time systems. The proposed Priority Time Petri Net gives determinism aspect to the model and accelerates its execution. Indeed, a compositional specification of a PTPN for complex application and multiprocessor architecture that solves the problem of hierarchy is presented.

Extending UML/MARTE-GRM for Integrating Tasks Migrations in Class Diagrams

There is a growing interest in modeling Real-Time Embedded Systems (RTES) using high-level approaches. The recent extension of Unified Modeling Language (UML) profile for Modeling and Analysis of Real-Time Embedded systems (MARTE) is enclosing a lot of stereotypes and sub-profiles providing support for designers to beat the shortcomings of complex systems development. In particular, the MARTE/GRM (Generic Resource Modeling) package offers stereotypes for annotating class diagrams with the needed information which will be extracted to fulfill a scheduling phase. However, GRM does not allow designers to specify data to be used neither in half-partitioned nor in global scheduling approaches; indeed, it does not support the modeling of task migration concept. Thus, we propose through this paper an extension of MARTE/GRM sub-profile to consider the modeling of information needed for the half-partitioned and global scheduling step.

A UML/MARTE-Based Design Pattern for Semi-partitioned Scheduling Analysis

The scheduling of Real-Time Embedded Systems (RTES) is a challenging step that requires vast knowledge and expertise about the domain, which makes difficult the step of complex systems scheduling modeling. This paper presents a design pattern intended to support and facilitate the scheduling modeling of multiprocessor systems. The contribution of this pattern is that is designed to i) support semi-partitioned scheduling allowing tasks migration ii) model all the tasks features/types and criteria of scheduling in the same view (only one pattern is used) iii) specify the system properties using a high-level modeling language UML/MARTE (Modeling and Analysis of Real-time and Embedded systems).

From UML/MARTE to RTDT: A model driven based method for scheduling analysis and HW/SW partitioning

Unified Modeling Language (UML) extensions for real time embedded systems (RTES) co-design are taking a growing interest by a great number of industrial and research communities. The extension mechanism is provided by UML profiles for RTES and it aims at improving an easily-understood method of system design for non-experts. One of the key items of the co-design methods is the Hardware/Software partitioning and scheduling tasks. Indeed, it is mandatory to define where and when tasks are implemented and run. Unfortunately, the main goals of co-design are not included in the usual practice of UML profiles. So, there exists a need for mapping used models to an execution platform for both schedulability test and HW/SW partitioning. In the present work, test schedulability and design space exploration are performed at an early stage. The proposed approach adopts Model Driven Engineering MDE. It starts from UML specification annotated with the recent profile for the Modeling and Analysis of Real Time Embedded systems MARTE. Following refinement strategy, transformation rules allow the finding of a feasible schedule that satisfies timing constraints and defining where tasks will be implemented. The overall approach is experimented on the design of a football player robot application.

Real-Time Design Patterns: Architectural Designs for Automatic Semi-Partitioned and Global Scheduling

The scheduling problem is becoming an important topic for different fields especially for Real-Time applications. Considering the complexity of Real-Time Embedded Systems (RTES) coupled with the variety of scheduling approaches and algorithms, the designer task is becoming increasingly hard. Few approaches have investigated design patterns to perform an automatic scheduling at a high-level of abstraction. However, only the partitioned scheduling that prevents task migrations has been taken into account. In this context, this paper proposes two design patterns maintaining an automatic choice of semi-partitioned and global scheduling algorithms. The Unified Modeling Language (UML) profile for the Modeling and Analysis of Real-Time Embedded systems (MARTE) is used to annotate the proposed design patterns with functional and non-functional properties.

Network Reconfiguration for Wireless Sensor Networks using UML/MARTE Profile.

The required autonomy and the growth of the complexity of wireless sensor networks (WSNs) systems give the reconfiguration a big importance. Thus, the integration of reconfiguration scenarios (node level or network level reconfiguration) in the development cycle of WSNs system is required to offer an efficient reaction to environment variability. In this direction, existing model based design approaches of reconfigurable WSNs are limited to the design of behavioral reconfiguration techniques which bring adjustment of the system’s parameters or update some functionalities. However, network reconfiguration which presents an important ability of networked systems for dealing with the network disconnectivity and power consumption, is still under-explored. In this context, we propose a high level model based design of WSNs applications using the UML/MARTE standard to specify network reconfiguration semantics. We define a new package named «NW_ Reconfiguration». A case study on water distribution network is proposed to evaluate our proposed design approach.

Patterns System for the Design of Partial Reconfigurable Applications on FPGA.

During the last few years, the Dynamic Partial Reconfiguration (DPR) has been introduced to the embedded systems as a key technique that aims at improving the flexibility of Field-Programmable Gate Array (FPGA)-based system reconfiguration. However, the design of these systems is a hard task using low-level functions where the design of the hardware side precedes that of the software. Recently, Model-Driven Engineering (MDE) based approaches have emerged. They aim at simplifying the modeling of the dynamically set systems and keep a design flow where DPR application and architecture are designed in parallel. In fact, there is a lack of reusable and generic models that allow the improvement of the designers’ task and the decrease of the development costs. In order to overcome these issues we propose in this paper an additional featuring or abstraction level in the DPR design flow introduced by these approaches. Our aim is to suggest for designers a method (process and models) which allows reusing recurrent application models and sharing experience-owned knowledge. The proposed method is a patterns system which is a combination of architectural and behavioral patterns dedicated to the Dynamic Partial reconfigurable RealTime Embedded (DP-RTE) systems.

From UML/MARTE Models of Multiprocessor Real-time Embedded Systems to Early Schedulability Analysis based on SimSo Tool

The increasing complexity of Real-Time Embedded Systems (RTES) should be met with equally sophisticated design methods. The recent Unified Modeling Language (UML) profile for Modeling and Analysis of RealTime Embedded systems (MARTE) is well adapted for systems modeling. However along with the variety of schedulability analysis tools, bridging the gap between design models and meta-models of the documented scheduling analysis tools becomes an important issue. In this paper, we discuss a Model To Text (M2T) transformation for enabling the derivation of schedulability analysis models from UML/MARTE models. The generated model for schedulability analysis represents an input for an analysis tool. As a proof of concepts, we present the implemented code and experimental results.