Muh-Tian Shiue

A low power and variable-length FFT processor design for flexible MIMO OFDM systems

In this paper, we present a low power and variable-length design of fast Fourier transform (FFT) processor for flexible MIMO-OFDM applications. In this work, mixed-radix-2/4/8 algorithm and new continuous-flow method are applied to achieve variable-length of 1K/2K/4K/8K points and in-order output. Furthermore, ping-pong cache memory architecture and optimized data scaling strategy are also applied to reduce main memory accesses up to 50% and achieve higher SQNR requirements of 16/64-QAM signals for multi-standards. A test chip of the proposed FFT processor has been designed and fabricated using CMOS 0.18µm 1P6M process with the core area of 4.96mm2. Our proposed processor can perform four independent data sequences of 2048-point FFT within 205.2 µs at operating clock rate of 20 MHz. The power consumption of calculating single 8192-point FFT sequence is only 20.88mW at operating clock rate of 10 MHz.

Design and Implementation of Power-Efficient K-Best MIMO Detector for Configurable Antennas

In this brief, a power-efficient multiple-input multiple-output (MIMO) detector that can flexibly support multiple antenna configurations and modulations is presented. This detector uses a sorting-free K-best algorithm named distributed K-best (DKB) algorithm and successive interference cancellation (SIC) to decrease computational complexity. The DKB and SIC schemes are designed as several elementary building blocks. Then, the antenna configurable architecture can be flexibly constructed by these elementary blocks. The multistage hardware architecture is proposed to achieve that only K clock cycles are required to find out the best K candidates, and the sorting circuit for the conventional K-best algorithm is avoided in our design. In addition, a shift multiplier which simply uses bit shift and additions is applied to replace the conventional multiplier for further reducing power consumption. The proposed configurable MIMO detector has been fabricated in 90-nm CMOS technology with core area of 0.7744 mm2. For 8 × 8, 64-QAM, and K = 10 configuration, the proposed chip achieves 489-Mb/s throughput rate with 17-mW power consumption at 102-MHz operating frequency and 1 V supply voltage. The performance results show that the proposed design has better power efficiency and antenna configurability than other related works.

DHT-Based OFDM System for Passband Transmission Over Frequency-Selective Channel

In this letter, a multicarrier modulation transceiver based on discrete Hartley transform (DHT) is investigated. The diagonalization of channel matrix is an important feature for the DFT-OFDM system. However, the conventional DHT-OFDM system cannot directly diagonalize the multipath fading channel so that the intercarrier coupling (ICC) effects will occur. To deal with this problem, we devise a new DHT-based OFDM architecture that can perfectly diagonalize the channel matrix by using the complementary property of DHT matrix. In addition, two-dimensional complex signaling, such as quadrature amplitude modulations (QAM), can also be applied to the proposed structure for bandwidth efficient transmission. The compatibility of DFT-OFDM and DHT-OFDM systems is also considered. Finally, numerical simulations shows the validity of the proposed DHT-based OFDM system.

High throughput concurrent lookahead adaptive decision feedback equaliser

A time-domain adaptive decision feedback equaliser (ADFE) for multi-gigabit wire-line 2-pulse amplitude modulation (PAM) communication systems is proposed. The throughput rate of a conventional ADFE is limited by the loops in the circuit. This investigation develops two methods for breaking or virtually breaking these loops. The first is the method of batch mode coefficient updating (BMCU), and the second is the concurrent lookahead (CLA) method. Since the loops are broken or virtually broken, a pipeline and/or a parallel method can be applied to design a throughput-rate-unlimited ADFE. The results of a simulation of the 10GBASE-S system reveal that the proposed BMCU-based CLA ADFE has the same average signal-to-noise ratio (SNR) as the original sequential ADFE for multi-mode fibres of length 30–90 m.

A VLSI design of dual-loop automatic gain control for dual-mode QAM/VSB CATV modem

A digitized automatic gain control (DAGC) whose loop bandwidth can be automatically regulated by a digital quantizer is presented in this paper. The designed quantizer that only costs tens of gates provides the DAGC both with wide loop bandwidth for fast acquisition and narrow loop bandwidth for low AGC gain jitter in stable steady-state. The receive bandpass filter, variable gain amplifier (VGA), and digital control circuits have been implemented in VLSI using 0.8 /spl mu/m CMOS technology. For both 64-QAM and 8-VSB signals, the closed-loop experimental results show that the designed DAGC has input dynamic range from 229 mV/sub pp/ to 456 mV/sub pp/, transient mode bandwidth 1 kHz, steady-state bandwidth 90 Hz, settling time of step response less than 2 ms using 10 MHz clock for digital control chip.

10Gbps decision feedback equalizer with dynamic lookahead decision loop

Decision feedback equalizer (DFE) uses a feedback path to cancel post-cursor ISI, and this feedback path will also cause the limitation of its maximum throughput rate. This paper proposes a new lookahead method to break the feedback path for multi-gigabit DFE design. After lookahead computation, each paralleled sub-circuit has the same throughput rate as original one. Therefore, the total throughput rate is proportional to the parallelization factor. The computation complexity of the proposed architecture is lower than that of multiplexer-based lookahead DFE if the tap number of the feedback filter is large. It is shown that the new method saves 10% hardware complexity for an 8 taps feedback filter DFE and 98% hardware complexity for a 12 taps feedback filter DFE in comparison to a 10Gbps multiplexer-based lookahead DFE.

A new VSB modulation technique and shaping filter design

In this paper, we propose a new approach for VSB modulation. A pair of complex digital filters are used to accomplish waveform shaping and VSB modulation simultaneously. By the use of longer tap length, the high stop band attenuation eliminates the need for SAW filters at the output stage. To verify our approach, we use the Zenith VSB HDTV system as a test vehicle. A pair of 79-tap raised cosine digital filters are derived, implemented, and tested.

A hardware efficient 64-QAM low-IF transceiver baseband for broadband communications

This paper presents a hardware efficient VLSI design of digital baseband for 64-QAM communication systems over the last-mile cable network. This VLSI system design involves a cost-efficient architecture of the adaptive equalizer and a two-phase linear architecture of the pulse shaping filters, which reduce the hardware requirement by a factor of four comparing with traditional quadrature direct form FIR filters. In this design, the two-fold carrier recovery loop possesses a pull-in range of /spl plusmn/100kHz (i.e. /spl plusmn/18, 500ppm of the symbol rate) and -82dBc jitter suppression. Based on the proposed multi-staged LMS-based fractionally-spaced equalizer, the receiver realizes the symbol spaced timing recovery in a /spl plusmn/200ppm tolerance of the symbol rate. The acquisition time of the proposed 64-QAM blind adaptive system is 7ms, and the transceiver reaches the operation speed of the case for 32.28Mb/s 64-QAM low-IF digital CATV system over NTSC 6MHz bandwidth channels. Using 0.35 /spl mu/m CMOS technology, the transceiver design occupies a chip area 5.5mm /spl times/ 5.5mm and power consumption 1.35W (1.0W for RX) when the power supply is 3.3V.

Design of antenna-configurable MIMO detector with high speed sorting architectures

In this paper, we propose an improved antenna-configurable MIMO detector combining with a high speed sorting architecture. The Codebook Enumeration (CBE) is applied to take advantages in multiple antenna configurations and signal modulations. The Parallel-Slice Merge Algorithm (PSMA) and Parallel Bubble-Slice Sort (PBSS) are also adopted to accelerate sorting speed. The proposed design applies pipelined architecture to speed up the operational frequency. Furthermore, Shift-Multiplier (SM) is also applied to reduce the critical timing path and circuit complexity. The proposed hardware circuit is realized in 90nm CMOS technology, and can operate at the maximum frequency 281MHz and the power consumption is 54.66mW.

A low complexity real-valued kernel DHT-based OFDM modulator/demodulator design

In this paper, a novel real-valued orthogonal frequency-division multiplexing (OFDM) modulator/demodulator based on discrete Hartley transform (DHT) is presented and implemented for the application in IEEE 802.11a/g wireless LAN. The proposed DHT-based architecture employs two real-valued fast DHT (FHT) kernel instead of the conventional complex-valued fast Fourier transform (FFT) for OFDM systems. By taking advantage of the real-valued operation of FHT, this approach can reduce the number of multiplications compared with the radix-2 FFT. Moreover, the DCT-based radix-2 FHT algorithm is realized to reduce the multiplications of conventional radix-2 FHT. The proposed real-valued DHT-based modulator/ demodulator has been designed and fabricated in a 0.18-µm CMOS technology with a core area of 928×935 µm2. The average power consumption is about 20.16 mW at 20MHz and 1.8 V supply voltage.