Muhammad H. Rais

FPGA design and implementation of fixed width standard and truncated 6×6-bit multipliers: A comparative study

This paper presents a comparative study of Field Programmable Gate Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc. Significant reduction in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. The power and area of truncated 6×6-bit multiplier shows significant improvement as compared to standard 6×6-bit multiplier. For Xilinx Spartan-3AN (XC3S700ANFGG484-5) FPGA device, truncated multiplier shows a reduction in power and area by 45% and 67% respectively as compared to standard multiplier.

FPGA implementation of Rijndael algorithm using reduced residue of prime numbers

This paper describes the Field Programmable Gate Array (FPGA) implementation of Rijndael algorithm based on a novel design of S-Box built using reduced residue of prime numbers. The objective is to present an efficient hardware implementation of Rijndael using very high speed integrated circuit hardware description language (VHDL). The novel S-Box look up table (LUT) entries forms a set of reduced residue of prime number, which forms a mathematical field. The S-Box with reduced residue of prime number adds more confusion to the entire process of Rijndael and makes it more complex and immune to algebraic attacks. The target hardware used in this paper is state-of-the-art Xilinx Virtex-5 XC5VLX50 FPGA. The proposed design achieves a throughput of 3.09 Gbps using only 1745 slices.