Syed Manzoor Qasim

An overview of advanced FPGA architectures for optimized hardware realization of computation intensive algorithms

Algorithms used in signal and image processing applications are computationally intensive. For optimized hardware realization of such algorithms with efficient utilization of available resources, an in-depth knowledge of the targeted field programmable gate array (FPGA) technology is required. This paper presents an overview of the architectures and technologies used in modern FPGAs. A case study of most popular and widely used state-of-the-art commercial FPGA technologies from Xilinx and Altera is also presented. Three-Dimensional (3D)-FPGA architecture is also discussed.

Field programmable gate array-based design and realisation of automatic censored cell averaging constant false alarm rate detector based on ordered data variability

The design and field programmable gate array (FPGA)-based realisation of automatic censored cell averaging (ACCA) constant false alarm rate (CFAR) detector based on ordered data variability (ODV) is discussed here. The ACCA-ODV CFAR algorithm has been recently proposed in the literature for detecting radar target in non-homogeneous background environments. The ACCA-ODV detector estimates the unknown background level by dynamically selecting a suitable set of ranked cells and doing successive hypothesis tests. The proposed detector does not require any prior information about the background environment. It uses the variability index statistic as a shape parameter to accept or reject the ordered cells under investigation. Recent advances in FPGA technology and availability of sophisticated design tools have made it possible to realise the computation intensive ACCA-ODV detector in hardware, in a cost-effective way. The architecture is modular and has been implemented and tested on an Altera Stratix II FPGA using Quartus II software. The post place and route result show that the proposed design can operate at 100-MHz, the maximum clock frequency of the prototyping board and for this frequency the total processing time required to perform a single run is 0.21--s. This amounts to a speedup for the FPGA-based hardware implementation by a factor of -110 as compared to software-based implementation, which takes 23--s to perform the same operation.

A proposed FPGA-based parallel architecture for matrix multiplication

Matrix multiplication is a computation intensive operation and plays an important role in many scientific and engineering applications. For high performance applications, this operation must be realized in hardware. This paper presents a parallel architecture for the multiplication of two matrices using field programmable gate array (FPGA). The proposed architecture employs advanced design techniques and exploits architectural features of FPGA. Results show that it provides performance improvements over previously reported hardware implementation. FPGA implementation results are presented and discussed.

A review of FPGA-based design methodology and optimization techniques for efficient hardware realization of computation intensive algorithms

Field programmable gate arrays (FPGAs) have emerged as platform of choice for efficient hardware realization of computation intensive algorithms because of their intrinsic parallelism and flexible architecture. However, to achieve high performance, FPGA must be supported by efficient design methodology and optimization techniques. In this paper, FPGA-based design methodology and optimization techniques that can be employed to obtain area, speed and power efficient circuits are reviewed and presented.

Single chip FPGA based realization of arbitrary waveform generator using rademacher and walsh functions

Arbitrary waveform generators (AWGs) are becoming increasingly important for test and measurement applications. This paper describes a new approach for generating arbitrary waveforms using FPGA and a set of Rademacher and Walsh functions. Utilizing these orthogonal functions, any periodic waveform can be realized. Recent advancements in field programmable gate array (FPGA) technology have made waveform generation very easy and cost-effective. For demonstration purpose we used a custom defined arbitrary waveform that is a concatenation of trapezoidal, sinusoidal and triangular waveforms. Simulation results for the proposed AWG are presented. Topdown approach has been adopted to realize the waveform genera in Spartan-3 FPGA. Th e maximum clock frequency for this design is 24.944 MHz with a power consumption of 62 mW

A New Approach for Arbitrary Waveform Generation using FPGA and Orthogonal Functions

In this paper, a new approach for generating arbitrary digital waveforms using orthogonal functions and field programmable gate array (FPGA) is presented. The availability of high performance FPGAs and sophisticated design tools in the recent years has made it possible to realize computation-intensive parts of a design in very easy and cost-effective way. A custom defined arbitrary waveform is selected to demonstrate the proposed technique. This approach can be easily adapted for the generation of variety of other periodic waveforms. The target device used in this research is Virtex-4 (xc4vfx12-10sf363) FPGA. The maximum operating frequency for this design is 44.821 MHz and utilizes only 6% of total FPGA slices. The compact size of the circuit allows for more functionality to be integrated in the same chip

A NOVEL FPGA-BASED APPROACH FOR DIGITAL WAVEFORM GENERATION USING ORTHOGONAL FUNCTIONS

This paper presents a novel approach for the generation of periodic waveforms in digital form using Field Programmable Gate Array (FPGA) and orthogonal functions. The orthogonal function consists of a set of Rademacher–Walsh Functions, and utilizing these functions, virtually any periodic waveform can be synthesized. Recent technological advancements in FPGA and availability of sophisticated digital design tools have made it possible to realize high-speed waveform generator in a cost-effective way. We demonstrate the proposed technique for the successful generation of Trapezoidal, Sinusoidal, Triangular waveforms, and a complex version of these waveforms. Simulation results for the various waveforms implemented in Xilinx Spartan-3 (XC3S200-4FT256) FPGA are presented both in analog and digital forms, and validated in MATLAB. The designed circuit can be easily integrated as a module for System-on-Chip (SoC) for on-chip waveform generation

FPGA implementation of Rijndael algorithm using reduced residue of prime numbers

This paper describes the Field Programmable Gate Array (FPGA) implementation of Rijndael algorithm based on a novel design of S-Box built using reduced residue of prime numbers. The objective is to present an efficient hardware implementation of Rijndael using very high speed integrated circuit hardware description language (VHDL). The novel S-Box look up table (LUT) entries forms a set of reduced residue of prime number, which forms a mathematical field. The S-Box with reduced residue of prime number adds more confusion to the entire process of Rijndael and makes it more complex and immune to algebraic attacks. The target hardware used in this paper is state-of-the-art Xilinx Virtex-5 XC5VLX50 FPGA. The proposed design achieves a throughput of 3.09 Gbps using only 1745 slices.

Hardware realization of a novel Automatic Censored Cell Averaging CFAR detection algorithm using FPGA

In this paper we present hardware realization of a novel Automatic Censored Cell Averaging (ACCA) Constant False Alarm Rate (CFAR) detection algorithm based on Ordered Data Variability (ODV) using Field Programmable Gate Array (FPGA). This algorithm has been recently proposed in the literature for radar target detection in non-homogeneous environments. The unknown background level can be estimated by dynamically selecting a suitable set of ranked reference window cells and by doing successive hypothesis tests. The ACCA-ODV based CFAR detector does not require any prior information about the background environment and uses the variability index statistic as a shape parameter to reject or accept the ordered cells under investigation. Recent advancements in modern FPGAs and availability of sophisticated electronic design tools have made it possible to realize the ACCA-ODV CFAR detector in a cost-effective way. The designed hardware is modular and has been physically realized in Altera Stratix II FPGA device.

FPGA based architecture for the computation of fourth-order cross moments

Fourth-order cross moments are used in modern digital signal processing as a powerful analytical tool for the synthesis and analysis of signals and systems. Computing fourth-order cross moments from incoming time-series data is computationally intensive process and requires fast computing systems and parallel processing techniques to meet the real time processing requirement. An algorithm based on matrix-matrix product formulation is adopted in this paper. This paper presents an FPGA based design for high-speed computation of fourth-order cross moments. The proposed design is coded in VHDL and functionally verified by implementing it on Xilinx Virtex-II Pro FPGA chip. FPGA implementation results are presented. The proposed design operates at a maximum frequency of 101.812 MHz.