Muhammad Mun’im Ahmad Zabidi

IF estimation of FSK signals using adaptive smoothed windowed cross Wigner-Ville distribution

Time-varying signals such as frequency shift-keying (FSK) signals can be characterized by the instantaneous frequency (IF). From the estimated IF, it is possible to derive the signal modulation parameters such as the subcarrier frequencies and the symbol duration. If accurate time-frequency representation (TFR) is obtained, the cross time-frequency distribution (XTFD) provides an optimum solution to IF estimation over quadratic time-frequency distribution (QTFD). Thus, an adaptive XTFD is proposed, the adaptive smoothed windowed cross Wigner-Ville distribution (ASW-XWVD), for which the kernel parameters are estimated according to the signal characteristics and the choice of reference signal. The IF is estimated from the peak of the TFR and comparison is performed using the S-transform. The variance in the IF estimation using the proposed ASW-XWVD meets the Cramer-Rao lower bound (CRLB) at minimum signal-to-noise ratio (SNR) of -3dB, while the S-transform never meets the CRLB, even at SNR of 12dB. For practical applications, the ASW-XWVD is applied to the FSK signal in the high frequency (HF) band and is able to provide accurate TFR and IF estimates at SNR of 14dB.

Embedded vision systems for ship recognition

Maritime security includes reliable identification of ship entering and leaving a nations territorial waters. Automated systems that could identify a ship could complement existing electronic signal identification methods. The use of Forward Looking Infrared (FLIR) and Synthetic Aperture Radar (SAR) enables ship image acquisition round-the-clock but their cost and complexity means few installations are available. The use of lower cost embedded vision systems using visible light for surveillance in a low-bandwidth sensor network could complement existing surveillance methods to improve surveillance coverage. This paper presents an overview of automatic ship detection methods with a view towards embedded implementation of suitable algorithms on optical smart cameras. We present results on applying Hus moment invariants for feature extraction on several classification algorithms. We achieved accuracies of close to 80% using the KStar and multilayer perceptron classifiers in recognizing one of four ship classes.

Efficient Motion Estimation Algorithms for HEVC/H.265 Video Coding

This paper presents two fast motion estimation algorithms based on the structure of the triangle and the pentagon, respectively, for HEVC/H.265 video coding. These new search patterns determine motion vectors faster than the two Tzsearch patterns - diamond and square - that are built into the motion estimation engine of the HEVC. The proposed algorithms are capable of achieving a faster run-time with negligible video quality loss and increase in bit rate. Experimental results show that, at their best, the triangle and pentagon algorithms can offer 63 % and 61.9 % speed-up in run-time respectively compared to the Tzsearch algorithms in HEVC reference software.

Low complexity maritime surveillance video using background subtraction on H.264

Maritime surveillance video is crucial in monitoring the waters from seaborne threats. Maritime surveillance cameras typically operate by recording the designated areas for long hours, with most of the video storage recording empty sea and sky. Video compression efficiency can be improved by assigning moving objects in video frame as foreground objects and the rest of the frame as background. The background is then compressed at a higher compression ratio to achieve better compression without significant loss of image quality at the region of interest (ROI). This paper presents a method of improving the standard H.264 video coder to improve on compression rate and computation time for maritime surveillance applications.

QoS provisioning for real time services on DiffServ aware IPv6 optical network using IXP-2400 Intel Network

Providing Quality of Service (QoS) and Traffic Engineering (TE) capabilities in the internet is essential, especially in supporting the requirement of real- time traffic, as well as mission critical applications. Differentiated Services (DiffServ) is an emerging technology that provides QoS and traffic engineering features in Internet Protocol (IP) Network by programming the IXP2400 Intel Network Processor. Since the introduction of the network processors, there have been a number of network services developed based on the special-built, packet processing optimized programmable microprocessors. This paper is mainly concerns on how to deploy DiffServ in order to assess priority functionalities. A scheduling mechanism was developed on the IXP2400 network processor to provide QoS by maintaining priority of incoming packets based on criteria i.e. class of packets and traffic. The queuing mechanism improves the QoS of the traffic at the expense of some performance degradation. To reduce the performance degradation, a cache unit has been added into the operation of the QoS mechanism to cut down SRAM access during the lookup operation. A performance study was then carried out to evaluate the performance of the QoS mechanism after adding the cache unit. The overall speed is enhanced and delay is minimized. At the same time, the mechanism can be implemented on the ENP-2611 Evaluation Board to verify the functionality of the application on hardware.

VLSI Implmentation of a Fast Kogge-Stone Parallel-Prefix Adder

This paper presents a VLSI implementation of a high speed Kogge-Stone adder (KSA) using 0.18µm process technology. The adder is known to be one of the fastest adder architectures, and this is validated through a comparison with other adder architectures including the standard ripple carry adder and the carry look ahead adder. Furthermore, our KSA adder is also compared with a default optmized adder from the Artisan standard cell library. The adders are compared for bit widths of 8, 16, and 32. The adders are designed using Verilog and synthesized using both front-end and back-end tools, with complete validation and verification stages, including analysis for performance, power, and area. Results show that in terms of performance, KSA results in the lowest propagation delay with almost constant delay for all bit widths, with up to 70% less delay as compared to all other architectures. Area and power penalty is found to also increase by roughly 59%. In terms of energy usage, the KSA adder results in up to 64% less. In the case when speed and energy are critical, this fast and energy efficient KSA adder can be readily integrated into custom VLSI designs.

Adaptive search window for low complexity surveillance video coding

Static video surveillance is an effective tool for maintaining security. Videos from stationary cameras contain mainly background, with movement appearing rarely. Standard video coders record everything in the video frames at the same quality, including the background which contains no information of interest. Knowledge of the application could improve the video compression efficiency. Standard video encoders takes a lot of computation power, with Motion Estimation (ME) taking around 60-80% of the encoder compute budget. Encoder computation cost can be reduced by encoding the background region at lower quality. This paper proposes the use of adaptive search window to reduce the search range to achieve the objective of lowering computation complexity.

QoS provisioning for real time services for IPv6 DiffServ network using IXP-2400 intel network processor

Providing quality of service (QoS) and traffic engineering (TE) capabilities in the Internet is essential, especially in supporting the requirement of real- time traffic, as well as mission critical applications. differentiated services (DiffServ) is an emerging technology that provides QoS and traffic engineering features in IP network by programming the IXP2400 Intel Network Processor. Since the introduction of the network processors, there have been a number of network services developed based on the special-built, packet processing-optimized programmable microprocessors. This paper is mainly concerns on how to deploy DiffServ in order to assess priority functionalities. A scheduling mechanism was developed on the IXP2400 network processor to provide QoS by maintaining priority of incoming packets based on criteria i.e. class of packets and traffic. The queuing mechanism improves the QoS of the traffic at the expense of some performance degradation. To reduce the performance degradation, a cache unit has been added into the operation of the QoS mechanism to cut down SRAM access during the lookup operation. A performance study was then carried out to evaluate the performance of the QoS mechanism after adding the cache unit. The overall speed is enhanced and delay is minimized. At the same time, the mechanism can be implemented on the ENP-2611 Evaluation Board to verify the functionality of the application on hardware.