Muhammad Nadzir Marsono

Biometric encryption based on a fuzzy vault scheme with a fast chaff generation algorithm

Fuzzy vault is a scheme that complements traditional cryptographic security systems by combining it with biometric authentication to overcome the security vulnerability inherent in cryptographic key storage. Biometric encryption systems based on fuzzy vault scheme are suitable for stand-alone security and authentication devices in the form of system-on-chip (SoC). However, the current fuzzy vault scheme has too many compute-intensive processes to make this feasible for SoC implementation. The most critical but compute-intensive function in the fuzzy vault scheme is the chaff generation which produces noise (chaff) points that hide the valid points inside the vault template. In this paper, we propose a new chaff generation algorithm which is computationally fast and viable for hardware acceleration by employing simple arithmetic operations. Complexity study shows that our algorithm has a complexity of O(n^2), which is a significant improvement over the existing method that exhibits O(n^3) complexity. Our experimental results show that, to generate 500 chaff points, the proposed algorithm gives a performance speed-up of over 140 times over existing Clancys algorithm. With the new chaff generation algorithm, it becomes much more amenable to implement the fuzzy vault scheme in the resource-constrained environment of system-on-chip.

Hardware Acceleration of OpenSSL Cryptographic Functions for High-Performance Internet Security

The Transport Layer Security (TLS) protocol is currently the predominant method of implementing Internet security. This paper proposes an FPGA-based embedded system integrating hardware that accelerates the cryptographic algorithms used in the SSL/TLS protocol. OpenSSL, an open source implementation of the SLL v3 and TLS v1 protocol, is deployed in the proposed embedded system powered with a Nios-2 embedded soft-core processor. Nios2-Linux RTOS is applied, which serves to provide Ethernet connectivity, multitasking, and support for the OpenSSL library. Key cipher functions used in SSL-driven connections, which include AES-256 symmetric encryption, SHA-2 hashing, RSA-2048 publickey cryptography, are accelerated in hardware. The embedded cryptosystem is prototyped completely on an Altera Stratix II FPGA development board. Experimental results show significant improvements in performance of the SSL transactions when the proposed embedded cryptosystem is deployed in the networking system.

Targeting spam control on middleboxes: Spam detection based on layer-3 e-mail content classification

This paper proposes a spam detection technique, at the packet level (layer 3), based on classification of e-mail contents. Our proposal targets spam control implementations on middleboxes. E-mails are first pre-classified (pre-detected) for spam on a per-packet basis, without the need for reassembly. This, in turn, allows fast e-mail class estimation (spam detection) at receiving e-mail servers to support more effective spam handling on both inbound and outbound (relayed) e-mails. In this paper, the naive Bayes classification technique is adapted to support both pre-classification and fast e-mail class estimation, on a per-packet basis. We focus on evaluating the accuracy of spam detection at layer 3, considering the constraints on processing byte-streams over the network, including packet re-ordering, fragmentation, overlapped bytes, and different packet sizes. Results show that the proposed layer-3 classification technique gives less than 0.5% false positive, which approximately equals the performance attained at layer 7. This shows that classifying e-mails at the packet level could differentiate non-spam from spam with high confidence for a viable spam control implementation on middleboxes.

Binary LNS-based naive Bayes hardware classifier for spam control

We propose a hardware architecture for a naive Bayes classifier in the context of e-mail classification for spam control. Our proposal presents a word-serial naive Bayes classifier architecture that utilizes the logarithmic number system (LNS) to reduce the computational complexity. We present the hardware architecture for non-iterative binary LNS recoding using a look-up table approach. Our design was synthesized targeting an Altera Stratix CPLD device. The synthesized classifier was functionally verified with a MATLAB implementation. Our binary LNS naive Bayes classifier exhibits high e-mail classification throughput of more than 30 thousands e-mails per second

Online NetFPGA decision tree statistical traffic classifier

Classifying online network traffic is becoming critical in network management and security. Recently, new classification methods based on analysis of statistical features of transport layer traffic have been proposed. While these new methods address the limitations of the port based and payload based traffic classification, the current software-based solutions are not fast enough to deal with the traffic of todays high-speed networks. In this paper, we propose an online statistical traffic classifier using the C4.5 machine learning algorithm running on the NetFPGA platform. Our NetFPGA classifier is constructed by adding three main modules to the NetFPGA reference switch design; a Netflow module, a feature extractor module, and a C4.5 search tree classifier. The proposed classifier is able to classify the input traffics at the maximum line speed of the NetFPGA platform, i.e. 8Gbps without any packet loss. Our method is based on the statistical features of the first few packets of a flow. The flow is classified just a few micro seconds after receiving the desired number of packets.

Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation

A hardware architecture for naive Bayes inference engine to classify e-mail contents for spam control is proposed. The inference engine utilises the logarithmic number system (LNS) to simplify naive Bayes computations. For high throughput LNS recoding, a non-iterative binary LNS recoding hardware architecture that uses look-up table approach is proposed. A noise model for the inference engine was developed and the noise bounds were analysed to determine the inference accuracy. The inference engine design is synthesised targeting the Altera Stratix field programmable gate array (FPGA) device. From the synthesis results, the binary LNS naive Bayes inference engine was found to have the capability to classify more than 117 million features per second, given a stream of a priori and likelihood probabilities as input with small computation noise. The synthesised inference engine was functionally verified against a MATLAB implementation.

Low latency network-on-chip router microarchitecture using request masking technique

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%-20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

A hardware architecture of Prewitt edge detection

This paper presents an efficient hardware architecture of Prewitt edge detection for high speed image processing applications. The hardware design is implemented by using Verilog hardware description language, whereas the software part is developed by using Matlab. The zero computational error analysis indicates that the proposed architecture produces similar outputs with ideal result obtained by Matlab software simulation. The architecture is capable of operating at a clock frequency of 145 MHz at 550 frames per second (fps), which implies that the system is suitable for both image processing and computer vision applications.

Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function

This paper presents the hardware implementation of an evolvable block-based neural network that utilizes a novel and cost efficient sigmoid-like activation function. Evolvable block-based neural networks (BbNNs) feature simultaneous optimization of structure, and viable implementation in reconfigurable digital hardware such as field programmable gate arrays (FPGAs). Efficient hardware implementation of BbNN structures is the primary goal of this paper. Various aspects of BbNN modeling and design considerations are presented. The neuron blocks are designed with properly described methodology, using only a single multiplier each, and implement a cost efficient sigmoid-like activation function. A novel method of reusing the multiplier to smoothly approximate a hyperbolic tangent (tanh) function to be used as the activation function for the neuron blocks is also presented. This is an important contribution, because a sigmoid-like activation function is provided at almost no additional cost. The neuron blocks are very cost efficient in terms of logic utilization when compared to the previous work. The BbNN is designed as an system-on-chip (SoC), and is functionally verified and tested on several case studies. The system performance allows real-time classification, and executes up to 410×faster than embedded software.

Network partitioning and GA heuristic crossover for NoC application mapping

Network-on-chip (NoC) has been introduced as a promising on-chip communication architecture to support many IP (intellectual property) cores on a single chip. Application mapping of IP cores onto a NoC topology is considered as a NP-hard problem. The increasing number of IP cores makes NoC application mapping more challenging to obtain optimum core-to-topology mapping. This paper proposes a genetic algorithm approach that incorporates network partitioning and heuristic crossover techniques to improve the NoC application mapping. Our experiment on VOPD (video object plane decoder) shows that our proposed method results in only 0.2% to 0.8% communication cost difference compared to global optimal mapping and 6% better communication cost compared to technique using conventional GA.