Mukunda B. Das

The effects of contact size and non-zero metal resistance on the determination of specific contact resistance

Abstract This paper presents theoretical and experimental results concerning two sources of error in the determination of specific contact resistance of ohmic contacts to semiconductor device structures that utilize circular test patterns with varying gap length. It is shown that the potential drop vs gap length data cannot be usually represented by a straight line and a non-zero metal overlay sheet resistance can significantly alter the effective contact resistance value.

High-frequency performance limitations of millimeter-wave heterojunction bipolar transistors

Heterojunction bipolar transistor structure (HBTs) with 0.25-, 0.4-, and 0.6- mu m emitter stripe widths and ultrasubmicrometer base widths, which are designed to achieve minimum transit time and low parasitic effects, are examined for their millimeter-wave performance. In particular,the dependence of the unity current gain frequency (f/sub tau /), the maximum oscillation frequency (f/sub max/), and the stability of power gains on the device structure and material parameters are critically analyzed. It is shown that the classical f/sub max/ expression commonly used for bipolar transistors, involving the effective carrier transit time and the collector-based RC time constant does not adequately represent the performance of ultrasubmicrometer-based-width HBTs, where the transadmittance phase delay associated with the collector-base depletion layer transit time and the parasitic collector-based capacitance are significant. The expected ballistic and quasiballistic behaviour of electron in these ultrasubmicrometer structures, if properly designed, minimizes the effective carrier transit time effect, but its impact on the f/sub max/ by the excess transadmittance phase delay poses a more fundamental and serious high-frequency limiting factor for the realization of millimeter-wave HBTs than has been hitherto recognized. The accuracy and usefulness of the proposed analytical approach is demonstrated for a practical HBT structure with 1.2- mu m emitter stripe design, giving results that agree well with measurements. >

A high aspect ratio design approach to millimeter-wave HEMT structures

In MESFET and HEMT structures as the gate length is reduced below 0.5 µm in an attempt to achieve amplification at highest possible frequencies, it is essential that the depletion depth under the gate be also reduced in order to preserve a high aspect ratio that ensures a high device voltage gain factor (gm/g0) and a reasonable value of stable power gain at high frequencies. Results based on this design approach indicate that an n-A1GaAs/GaAs HEMT structure with 0.25-µm gate length could provide stable power gain in excess of 6 dB at the unity current gain frequency of 92.4 GHz, and for an aspect ratio of ten it is difficult to reduce the gate length below 0.25 µm.

Extraction of high-frequency equivalent circuit parameters of submicron gate-length MOSFET's

As the effective gate-length of a MOSFET reduces, its high-frequency characteristics improve. However, they become more difficult to model. Current SPICE models are based on DC measurement data and simplistic capacitance models which can only approximate the high-frequency device characteristics up to a fraction of the device unity current gain frequency (f/sub /spl tau//). Thus, it is important to investigate the high-frequency characteristics and then incorporate the small-signal equivalent circuit parameters in SPICE. In this, work we report a simple nonquasi static model, which offers good accuracy needed for circuit simulation, and a new curve fitting method for the extraction of the network model elements. The current work is part of a study aimed at improving the existing scalable model for MOSFETs, and it focuses on extracting the elements of an equivalent circuit which describes the state-of-the-art device.

The characteristics of AuGe-based ohmic contacts to n-GaAs including the effects of aging

Abstract We have investigated and compared the characteristics of Au:Ge, Ni/Au:Ge and Au/Ni/Au:Ge ohmic contact metallizations to ion-implanted and epitaxial n -GaAs layers on semi-insulting substrates. Auger depth profiles of ohmic contacts and SEM of surface microstructures have provided significant insight as to the nature and degradation mechanism of ohmic contacts with aging. An electrolytic tank model with distributed resistors representing nodular or cluster form contacts has been successfully used to understand the effects of non-uniform ohmic contacts. A small degree of change in the semiconductor sheet resistance in the gaps between contacts, with aging at an elevated temperature, has been attributed to possible lateral surface diffusion of Au in the Au:Ge contacts and Ge in the Ni/Au:Ge and Au/Ni/Au:Ge contacts.

Measurements and interpretation of low-frequency noise in FET's

Equivalent gate-noise voltage magnitudes of MOSFETs and JFETs have been measured by a direct method for the frequency range of 20 Hz-9 kHz. Results of a number of theoretical analyses of MOSFET flicker noise have been combined to yield a generalized expression for the drain-noise current. Experimental results showing the bias, temperature, and frequency dependence of the noise have been presented and carefully examined in cognizance with the divergent nature of various theories and relevant published experimental data.

Measurement and comparison of 1/f noise and g-r noise in silicon homojunction and III-V heterojunction bipolar transistors

This paper experimentally determines and compares the 1/f noise and the g-r noise, as components of the base noise current spectral density, in Si homojunction and III-V heterojunction bipolar transistors (HBTs) in common-emitter configuration. The noise spectra for each of these devices are obtained as functions of the base bias current (I/sub B/), and the 1/f noise has been found to depend on I/sub B/ as I/sub B//sup /spl gamma//, where /spl gamma//spl sim/1.8 for the silicon BJTs and InP/InGaAs HBTs with high current gains (/spl beta//spl sim/50), and /spl gamma//spl sim/1.1 for the AlGaAs/GaAs HBTs with low current gains (4</spl beta/<12). The nearly constant current gain and the near square-law and inverse-square emitter area dependence of 1/f noise in silicon devices are indicative of the dominant base bulk recombination nature of this noise. The 1/f noise in the InP based HBTs has been found to be lowest among all the devices we have tested, and its origin is suggested to be the base bulk recombination as in the Si devices. For the AlGaAs/GaAs HBTs, the low current gain and the near unity value of /spl gamma/, arise most likely due to the combined effects of surface, bulk, and depletion region recombinations and the base-to-emitter injection. The dependence of the 1/f noise on the base current density in the devices tested in this work, and those tested by others are compared to find out which HBTs have achieved the lowest level of 1/f noise.

Noise behavior of 1-&#181;m gate-length modulation-doped FET's from 10 -2 to 10 8 Hz

Measured equivalent gate noise voltage spectra of 1-µm gate-length MODFETs, for the frequency range of 0.01 Hz-100 MHz, are presented. They indicate that the noise consists of several high-intensity trap-related generation-recombination (g-r) noise components superimposed on a background1/fnoise. The g-r noise is reduced when the Al mole-fraction is lowered. The same occurs when the gate reverse bias is increased. At 100 K the g-r noise bulge moves towards subaudio frequencies clearly revealing the1/fnoise.

Determination of carrier saturation velocity in short-gate-length modulation-doped FET'S

Based on a combined carrier saturation velocity/charge-control model, measured drain saturation current, small-signal transconductance and channel conductance data have been analyzed with consistency for the determination of the effective carrier saturation velocity using 1-µm gate-length MODFETs. The results demonstrate the validity of the model in the mid-range of gate bias voltage and indicate the extent of deviations that occur due to different physical processes in the lower and higher gate bias ranges.

Design calculations for submicron gate-length AlGaAs/GaAs modulation-doped FET structures using carrier saturation velocity/charge-control model

Abstract dc and small-signal ac characteristics of AlGaAs/GaAs modulation-doped FETs have been calculated by combining the conventional charge-control model with the carrier velocity saturation concept in realistic submicron gate structures. For the desired threshold voltage and the maximum gate voltage swing, the designer basically selects the thickness of the n -AlGaAs layer, for the preferred doping concentration, from the design graphs provided. Representative theoretical I/V characteristics and saturation current and transconductance versus gate voltage graphs are presented for the 0.25 μm and 0.8 μm gate-length structures with and without the presence of source and drain series resistances.