Jau-Wen Chen

Chip-level simulation for CDM failures in multi-power ICs

This paper presents a new chip-level simulation methodology for charged-device model (CDM) failure analysis in multi-power ICs. A circuit model considering reported CDM failures and efficient simulation is proposed and incorporated with the circuit-level ESD simulator, iETSIM. The CDM behaviors in multi-power ICs are analyzed and the vulnerable sites to CDM stress can be predicted by chip-level simulation. Simulation results are verified by CDM testing of a 0.25 /spl mu/m CMOS ASIC and show good correlation. This simulation methodology at the full-chip level enables us to address CDM failure issues before the detailed chip floorplan and power grid networking are started.

ESD design rule checker

Electrostatic discharge (ESD) protection circuitry is essential for every I/O cell design and has its own set of design rules. These design rules are not only complex but also beyond the scope of commercial DRC tools. In this paper, we present the framework of our ESD design rule checker, and address some of the open issues in the ESD design rule checker presented by Sinha et al. (1998).

Full chip ESD design rule checking

Electrostatic discharge (ESD) protection is essential for reliability and high yield. ESD design rule checking, however, is beyond the scope of commercial DRC tools. We have presented previously an ESD design rule checker for individual I/O cells. Full chip ESD design rules come in a myriad number of ways and are heavily process dependent. To check them one by one requires rewriting the design rule checker program for each process generation. This paper presents a framework for full chip ESD design rule checking adaptive to how full chip ESD design rules are derived.

ESD-induced internal core device failure: new failure modes in system-on-chip (SOC) designs

With MOSFET scaling, increased design complexity, and multiple system power domains, ESD failures occur in internal core areas which are not connected to external package pins. A review of the various internal core device failure mechanisms and design recommendations are presented.

The effects of substrate coupling on triggering uniformity and ESD failure threshold of fully silicided NMOS transistors

We present a multi-finger turn-on model incorporating substrate coupling effects in multi-finger NMOS transistors during ESD events. It is demonstrated that the substrate coupling enables uniform triggering in a multi-finger structure. In addition, we show that fully silicided transistors can be used successfully as an ESD protection device without any design/process options if the effective epi thickness is larger than 1.5 /spl mu/m or bulk wafer is used.

Investigations of Salicided and Salicide-Blocked MOSFETs for ESD Including ESD Simulation

Standard salicided MOSFETs have been repeatedly shown to have inferior ESD protection properties in comparison to salicide-blocked MOSFETs. Standard explanations typically attribute this to shallower current flow and higher peak current density in salicided devices due to the higher conductivity of salicides. In this work we present a numerical analysis of the phenomenon using physical mixed-mode circuit-device simulation. Our results show that the inherent lack of thickness uniformity known to exist in salicide layers can lead to local concentration of current flow and thus local failure of the device.