Munawar Agus Riyadi

The channel mobility degradation in a nanoscale metal–oxide–semiconductor field effect transistor due to injection from the ballistic contacts

The ballistic mobility degradation is shown to originate from nonstationary (transient) transport in response to the ohmic electric field. The source and drain reservoirs launch electrons into the channel with injection velocity transiting the channel with finite ballisticity defined as the probability of a collision-free flight. The distinction is made between the ballistic mean free path and that present in a long channel. The results are in excellent agreement with those obtained from Monte Carlo procedures and experiments.

Temperature-dependent ballistic transport in a channel with length below the scattering-limited mean free path

The temperature-dependent ballistic transport, using nonequilibrium Arora distribution function (NEADF), is shown to result in mobility degradation with reduction in channel length, in direct contrast to expectation of a collision-free transport. The ballistic mean free path (mfp) is much higher than the scattering-limited long-channel mfp, yet the mobility is amazingly lower. High-field effects, converting stochastic velocity vectors to streamlined ones, are found to be negligible when the applied voltage is less than the critical voltage appropriate for a ballistic mfp, especially at cryogenic temperatures. Excellent agreement with the experimental data on a metal-oxide-semiconductor field-effect transistor is obtained. The applications of NEADF are shown to cover a wide spectrum, covering regimes from the scattering-limited to ballistic, from nondegenerate to degenerate, from nanowire to bulk, from low- to high-temperature, and from a low electric field to an extremely high electric field.

Low-dimensional carrier statistics in nanostructures

The carrier statistics in a low-dimensional nanostructure with length in one or more of the three dimensions plummeting below carriers De Broglie wavelength is investigated. The probability distribution, the Fermi level, intrinsic velocity, and energy of the carriers are sternly affected on reducing dimensionality from 3-dimensional (3-D) bulk configuration. The carrier statistics for degenerate and non-degenerate regimes for nanostructures is worked out with an emphasis to predict the ultimate carrier velocity in a high electric field. The general results presented are applicable to all materials once the carrier concentration and ambient temperature are identified

Vertical double gate MOSFET for nanoscale device with fully depleted feature

A fully depleted vertical double gate MOSFET device was revealed with the implementation of oblique rotating implantation (ORI) method in 25 nm silicon pillar thickness. Several devices with various gate lengths (20–100 nm) were simulated and evaluated using virtual wafer tool. The implication of gate length reduction on the short channel effect (SCE) shows considerable advantages with higher current drives at lower gate length, while the low subthreshold swing could balance the threshold voltage roll‐off in the term of increasing power consumption. As a result, the drive current and also SCE controllability will be a benefit in the fully depleted device.

Silicon pillar thickness effect on vertical double gate MOSFET (VDGM) with oblique rotating implantation (ORI) method

The silicon pillar thickness effect on vertical double gate MOSFET (VDGM) fabricated by implementing oblique rotating ion implantation (ORI) method is investigated. For this purpose, several silicon pillar thicknesses tsi were simulated. The source region was found to merge at tsi < 57 nm, forming floating body effect. The electron-hole concentration along the channel and the depletion isolation region shows different shape and broaden in smaller tsi. For several channel lengths Lg les 100 nm, in the reduction of pillar thickness, the subthreshold slope (SS) tends to decrease, which indicate an increase in gate-gate charge coupling. Other short channel effect parameters (Ioff, IDsat) show better improvement for lower pillar thickness, thus offer better performance and control.

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Tole Sutikno, Lina Handayani, Deris Stiawan, Munawar Agus Riyadi, Imam Much Ibnu Subroto Department of Electrical Engineering, Universitas Ahmad Dahlan, Yogyakarta, Indonesia Faculty of Public Health, Universitas Ahmad Dahlan, Yogyakarta, Indonesia Department of Computer Engineering, Universitas Sriwijaya, Palembang, Indonesia Department of Electrical Engineering, Universitas Diponegoro, Semarang, Indonesia Department of Informatics Engineering, Universitas Islam Sultan Agung, Semarang, Indonesia

FPGA-based system for countinous monitoring of three vital signs of human body

This paper has major aim to design a low cost, low power, reliable, and easy to use biomedical instrumentation which can either monitoring or measuring three human body vital signs, i.e. body temperature, heart rate, and respiratory rate. The developed system uses a fingertip optical sensor to measure heart rate and thermistor to detect breathing and body temperature. The designed circuit was simulated using Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) and later synthesized into Spartan-3 FPGA development broad. The test result shows that the developed system successfully obtains 96% accuracy in measuring the three human body vital signs.

The depletion influence on the non-planar vertical MOSFET threshold voltage

The continuous scaling of transistors in nano scale leads to the invention of more sophisticated devices which may possess non-planar structures. As a consequence, the model for respective devices is of importance in order to predict the performance and behaviour throughout its operation. In non-planar structure, the thickness of silicon layer strongly affects the overall performance of the device. In this paper, we investigate the influence of depletion in the silicon layer of vertical MOSFET and develop an analytical model for devices with vertical pillar using parabolic approximation. The model for floating body channel structure which may form either partial or fully depleted channel was developed and elaborated as well. The simulation result shows the shift in threshold voltage characteristics with the different depletion widths and pillar thicknesses in the variation of channel length.

Analytical Analysis of Ballistic Drift Velocity in Low-dimensional Nano-devices

The analytical analysis of ballistic drift velocity for low-dimensional nanodevices was presented. The ballistic transport is predicted in the presence of high electric field for non-degenerate and degenerate regime. The saturation velocity is found to be ballistic regardless of the device dimensions. The intrinsic velocity limits this saturation velocity. It’s does not sensitively depend on the ballistic or scattering-limited nature of the mobility. In the degenerate realm, the saturation velocity is shown to be the Fermi velocity that is independent of temperature but strongly dependent on carrier concentration. In the non-degenerate realm, the intrinsic velocity is the thermal velocity that depends only on the ambient temperature.

Physics-Based Simulation of Carrier Velocity in 2-Dimensional P-Type MOSFET

The carrier velocity for 2-dimensional (2-D) p-type nanostructure was simulated in this paper. According to the energy band diagram, the effective mass (m*) in the p-type silicon is mostly dominated by heavy hole because of the large gap between heavy hole and light hole in k = 0. The carrier concentration calculation for 2-D, based on the Fermi – Dirac statistic on the order of zero ( ), was applied to obtain the intrinsic velocity of carrier, in the term of thermal velocity vth. The results for 2-D carrier velocity were modeled and simulated, and the comparison for degenerate and non-degenerate regime is presented for various temperature and concentration. It is revealed that the velocity is strongly dependent on concentration and becomes independent of temperature at high concentration.