Munehisa Takei

Channel strain analysis in high-performance damascene-gate p-metal-oxide-semiconductor field effect transistors using high-spatial resolution Raman spectroscopy

Channel strain analysis in damascene-gate p-metal-oxide-semiconductor field effect transistors (pMOSFETs) with a compressive stress liner and embedded SiGe after the dummy gate removal was studied using micro-Raman spectroscopy with a UV laser (λ=363.8 nm) and a quasiline excitation source. Using a quasiline excitation source, we obtained spatial and energy information simultaneously with a high spatial resolution in the one-dimensional strain profile. For Lgate>210 nm samples, we performed laser exposure for 10 min to measure the channel strain. However, the channel strain for Lgate<210 nm samples was impossible to evaluate due to the limitation of the spatial resolution. Therefore, we increased the laser exposure time to 40 min for Lgate<210 nm samples. Super invar metal with an extremely low thermal coefficient was installed in the monochromator, which achieved a very long measurement. Finally, we found an extremely large stress of −2.4 GPa in the channel of Lgate=30 nm samples. These results demonstra...

Study of Strain Induction for Metal–Oxide–Semiconductor Field-Effect Transistors using Transparent Dummy Gates and Stress Liners

Strain induction was studied on a sample that had a dummy gate tetraethyl orthosilicate–silicon dioxide (TEOS–SiO2) and SiN film by UV-Raman spectroscopy with high spatial and high wave-number resolution. The UV laser penetrated through the dummy gate that was transparent to UV light, which enabled us to evaluate strain in the channel of the metal–oxide–semiconductor field-effect transistor (MOSFET) model. Furthermore, we compared stress profiles obtained by finite element (FE) calculations with those obtained by UV-Raman measurements. There was a difference between the stress profiles in the line-and-space pattern sample and in the dummy-gate sample; large compressive (tensile) strains were concentrated at the channel edges in the dummy-gate sample with the compressive (tensile) stress liner, although both tensile and compressive strains existed at the channel edge in the line-and-space pattern sample. The results from UV-Raman spectroscopy were consistent with those obtained by the FE calculation.

Channel-Stress Enhancement Characteristics for Scaled pMOSFETs by Using Damascene Gate With Top-Cut Compressive Stress Liner and eSiGe

A damascene-gate process enhances the drivability in the shorter gate length region, as compared to a conventional gate-first process for pFETs with compressive stress SiN liners and embedded source/drain SiGe. The origin of the gate length effect for damascene-gate pFETs is studied by using UV-Raman spectroscopy and stress simulation. Moreover, the relationship between channel strain and channel width is analyzed, and the enhancement effect of the drivability on channel width is demonstrated. It is found that channel strain is considerably enhanced with the narrower channel width and shorter gate length by the process combination of the damascene gate and stress enhancement techniques. Owing to the enhancement effects of both channel width and gate length, a high drive current of 1090 muA/mum at Vds = Vgs = -1.0 V and Ioff = 100 nA/mum is achieved for the damascene-gate pFET with 0.3-mum channel width and 40-nm gate length.

Evaluation of Strained-Silicon by Electron Backscattering Pattern Measurement: Comparison Study with UV-Raman Measurement and Edge Force Model Calculation

We demonstrate the results of strain (stress) evaluation obtained from electron backscattering pattern (EBSP) measurement for samples of a strained Si-on-insulator (SSOI) and a Si substrate with a patterned SiN film. Two-dimensional stress distributions were obtained in 40×40 µm2 areas of the SSOI. The biaxial stress state was also obtained in the SSOI. Furthermore, clear cross-hatch contrast was observed, especially in the distribution of shear stress Sxy, in contrast to with the other distributions of normal stress Sxx and Syy. One- and two-dimensional stress distributions in the Si substrate with the patterned SiN film were also obtained from EBSP measurement. Moreover, the results were compared with those of UV-Raman measurement and edge force model calculation, and were found to have a good correlation with each other. EBSP measurement was used to measure the complicated biaxial stress including the shear stress in a sample with a 150-nm-wide space pattern. We can conclude that EBSP measurement is a useful method for precisely measuring stress with high spatial resolution.

Stress evaluation in thin strained-Si film by polarized Raman spectroscopy using localized surface plasmon resonance

We evaluated the stress in a thin strained-Si film on relaxed SiGe on a surface-oxidized Si substrate using surface enhanced Raman scattering (SERS). The strained-Si peak was enhanced by the SERS technique. However, the strained-Si peak shifted toward a higher wavenumber while the peaks from the Si substrate were unchanged. We performed Raman measurement under the optical geometry in LO and TO phonon active conditions. From these measurements, it was clarified that the peak shift was attributed to the TO phonon peak that appeared, which was caused by the excitation of the z polar component in the near-field light.

Mobility and Velocity Enhancement Effects of High Uniaxial Stress on Si (100) and (110) Substrates for Short-Channel pFETs

An experimental study of mobility and velocity enhancement effects is reported for highly strained short-channel p-channel field-effect transistors (pFETs) using a damascene-gate process on Si (100) and (110) substrates. The relationship between the mobility and the saturation velocity of hole under a compressive stress over 2.0 GPa is discussed. The local channel stress of 2.4 GPa is successfully measured with ultraviolet-Raman spectroscopy for the 30-nm-gate-length device with top-cut compressive-stress SiN liner and embedded SiGe. Mobility and saturation-velocity enhancements of (100) substrate are larger than those of (110) under the high channel stress. In consequence, the saturation current on (100) is larger than that on (110) for the pFETs with higher channel stress and shorter gate length. Moreover, the large enhancement rate of saturation velocity to mobility by the uniaxial stress suggests high injection velocity for the pFETs with the stressors since the high channel stress is induced near the potential peak of the source by using the damascene-gate technology.

Improvement of CVD SiO2 by Post Deposition Microwave Plasma Treatment

We evaluated density and chemical bonding states of the CVD SiO2 film with and without plasma treatment to clarify an effect of the plasma treatment. It was found that the chemical bonding states were homogenized by the plasma treatment from the results of X-ray photoelectron spectroscopy. In addition, an increase of the film density was also observed. These results indicate the densification of SiO2 film, suppression of bond-angle fluctuation, and decrease of impurities (e.g. Hydrogen, Nitrogen and so on) in the SiO2 film. These results can well explain the improvement of the electrical properties by the plasma treatment. Furthermore, UV-Raman measurement was performed to evaluate the modification of Si stress and crystal quality at the SiO2/Si interface.

Channel-stress study on gate-size effects for damascene-Gate pMOSFETs with top-cut compressive stress liner and eSiGe

Damascene gate process enhances the drivability in shorter gate length region, as compared to conventional gate 1st process for pFETs with compressive stress SiN liner and embedded SiGe. The origin of the gate length effect is investigated for the first time by using the UV-Raman spectroscopy. Moreover, the relationship between channel strain and gate width for damascene gate pFETs is analyzed and the effect is also demonstrated. It is found that channel strain is considerably enhanced in shorter gate length and narrower gate width by the combination of damascene gate process and stress enhancement techniques.

Study of stress effect on replacement gate technology with compressive stress liner and eSiGe for pFETs

The stress effect at the channel region of pFETs with compressive stress liner (c-SL) and eSiGe using replacement gate technology is firstly investigated in detail based on the combination of UV-Raman spectroscopy and 3D stress simulation. The gate length effect for the channel stress is confirmed by measurement and simulation. Moreover, the Ion dependence on the channel width is also investigated. It is found that the lateral stress along the channel is enhanced at the edge beside STI, resulting in high Ion at narrow gate width region.

Evaluation of phonon confinement in ultrathin-film silicon-on-insulator by Raman spectroscopy

Raman spectroscopy is a practical evaluation technique for the quantum effect of phonons in a microcrystalline structure. It is very sensitive to fluctuations of crystalline potential or localized atomic geometry. Phonon confinement is observed as a broadening and desymmetrization of the Raman spectrum. However, Raman spectra also include information on crystal quality, strain, and thermal influence caused by the excitation source. Because these factors have an effect similar to that of phonon confinement on spectra, distinction of the factors is essential for accurate evaluation of the phonon confinement effect. The influence of these effects in the utrathin-film silicon-on-insulator (SOI) was investigated by Raman spectroscopy. Marked broadening and desymmetrization of Raman spectra were confirmed for the SOIs with thickness less than 5 nm. The crystalline quality and strain in the SOI layer were investigated by X-ray diffraction. We developed a precise simulation technique for phonon confinement with consideration of thermal and strain effects. By comparing the simulation with the results of Raman spectroscopy, an exact evaluation of phonon confinement effects in utrathin-film SOI was achieved.