Munir M. El-Desouki

CMOS Image Sensors for High Speed Applications

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

High-Speed, Single-Photon Avalanche-Photodiode Imager for Biomedical Applications

The design of a low-light level pixel in CMOS technology for biomedical applications is described. This pixel is also suitable for very high-speed applications, such as fluorescence lifetime imaging (FLIM) used for drug discovery and/or minimally-invasive optical biopsy. In order to achieve high-speed imaging using single-photon detection, a detector with a very low dead-time is needed. The single-photon avalanche-photodiode (SPAD) discussed in this work uses a mainstream deep-submicron CMOS technology in order to achieve ultrahigh-speed operation and high pixel fill-factor, with in-pixel active quench and reset circuits. The paper also presents an innovative approach for reducing the deadtime of the detector and an attractive technique for simultaneous high-speed image acquisition by all the pixels of an array in parallel.

A low-power CMOS class-E power amplifier for biotelemetry applications

Designing efficient, fully integrated transceivers that could operate from very low supply voltages and for biomedical implantable electronic systems is a major challenge. This paper presents a fully integrated, 2.4 GHz class-E power amplifier (PA), with a class-F driver stage. The circuit was fabricated in a standard 0.18 /spl mu/m CMOS technology. Measurement results show a maximum drain efficiency of 38 % and a maximum gain of 17 dB. When operating from a 1.2 V supply, the PA delivers an output power of 9 mW with a power-added efficiency (PAE) of 33 %. The supply voltage can go down to 0.6 V with an output power of 2 mW and a PAE of 25 %. The circuit also has a second output to test the effects of using an on-chip filter in low-power designs. This work demonstrates the feasibility of using class-E PAs for short-range, low-power applications.

CMOS Active-Pixel Sensor With In-Situ Memory for Ultrahigh-Speed Imaging

State-of-the-art image sensor arrays have not been able to operate at frame rates that exceed tens to hundreds of thousands of frames per second. The main bottle neck preventing imaging at higher frame rates is the time required to access the array, convert the image data from analog to digital, and transmit the data off the image sensor chip. The later is considered the most significant source of delay, mainly due to the limited number of input and output ports available on the chip. This work allows for a significant increase in image capture rate by separating the image acquisition phase from the conversion and readout phase. This was done by capturing eight frames at a high capture rate and temporarily storing the multiple frames into analog memory units that are incorporated inside the pixel. The design was implemented in a deep-submicron CMOS 130 nm technology that allows for high-speed operation. This paper discusses the tradeoffs of using in-situ frame storage and gives some recommendations.

A Novel, High-Dynamic-Range, High-Speed, and High-Sensitivity CMOS Imager Using Time-Domain Single-Photon Counting and Avalanche Photodiodes

Avalanche photodiodes used in Geiger mode as single-photon counters have become very attractive imaging tools. High-speed single-photon imaging can be used in very low-light-level applications such as surveillance and security imaging, quantum computing, and biomedical imaging including bioluminescence and fluorescence lifetime imaging. However, a typical avalanche-based single-photon detector cannot offer the high dynamic range that is needed for many biomedical and surveillance applications. In this paper, we show how a single-photon detector can be used in time domain for high-dynamic-range applications. We also discuss novel techniques to implement the time-domain single-photon imager in mainstream deep-submicrometer CMOS technology. The designed imager offers high dynamic range and high sensitivity, while maintaining high-speed operation and low cost.

CMOS imaging for biomedical applications

CMOS photodetectors and imaging systems have shown that they possess adequate performance characteristics to replace CCDs or PMTs in some biomedical applications, thereby providing low power, portable, and cheap integrated bioimaging systems. Some advanced solutions, like novel active pixel sensors that detect ultra-low light levels, and avalanche photodiodes that are integrated in CMOS and perform single photon detection, are addressed in this paper.

The Impact of On-Chip Interconnections on CMOS RF Integrated Circuits

Achieving power- and area-efficient fully integrated transceivers is one of the major challenges faced when designing high-frequency electronic circuits suitable for biomedical applications or wireless sensor networks. The power losses associated with the parasitics of on-chip inductors, transistors, and interconnections have posed design challenges in the full integration of power-efficient CMOS radio-frequency integrated circuits (RF ICs). In addition, the parasitics of on-chip passive components that are integrated on lossy silicon substrates have made CMOS-based integrated circuits inferior to their compound-semiconductor counterparts. The parasitic effects of on-chip interconnections play a key role in RF circuit performance, particularly as the frequency of operation increases. Neglecting these effects leads to the significant degradation in circuit performance or even failure of operation in some cases. Furthermore, unlike transistors, miniaturization of interconnections does not improve their performance. This paper demonstrates the impact of metal layer resistivity and layout parasitics on an RF power amplifier (PA) and a low-noise amplifier (LNA). A nonlinear fully integrated 2.4-GHz class-E PA, with a class-F driver stage, and a 5-GHz LNA are discussed. The circuits were fabricated in a standard 0.18- mum CMOS technology. The layouts of the presented CMOS amplifiers were designed by carefully modeling the interconnection wires during the simulations and optimizing their widths for minimum parasitic effects and hence optimum measured circuit performance. Due to the careful layout design and interconnection optimization, the implemented amplifier circuits showed a good match between the measured and simulated performance characteristics.

Low-power integrated CMOS RF transceiver circuits for short-range applications

This paper discusses our efforts in designing different low-power RF transceiver blocks, starting with the LNA and power amplifier (PA). The paper discusses the effect of four different input matching methodologies on the gain of narrow-band LNAs. Measurement results of two LNAs fabricated in a 0.18 mum CMOS technology are also presented. Two ultra-wideband (UWB) LNA designs that aim for low- voltage and low-power operation are also discussed in this paper. The UWB LNAs consume a power of 5.8 mW from a 0.8 V supply voltage, while achieving a maximum gain of 12.5 dB and an input matching better than -10 dB from 2-10 GHz with a NF of 3.5 dB. A fully integrated, 2.4 GHz class-E PA, with a class-F driver stage is also discussed in this work, demonstrating the feasibility of using CMOS class-E PAs for low-transmit power applications. The circuit was fabricated in a standard 0.18 mum CMOS technology with a maximum drain efficiency of 53%. When operating from a 1.2 V supply, the PA delivers an output power of 14.5 mW with a power-added efficiency (PAE) of 51%. The supply voltage can go down to 0.6 V with an output power of 3.5 mW and a PAE of 43%. Finally, the paper also discusses a simple transmitter and receiver front-end, in addition to a single-block simplified, low- power PLL transmitter design.

A 0.65V CMOS power amplifier for biotelemetry applications

In order to reduce the power consumption in biomedical implantable electronic systems, there is a major demand on reducing the supply voltage. This paper presents a fully integrated, 650 MHz class-E power amplifier (PA), with a class-F driver stage that is suitable for low-voltage operation. The circuit was fabricated in a standard 0.18 mum CMOS technology. Measurement results show a maximum drain efficiency of 15% and a maximum gain of 11.5 dB. When operated from a 0.65 V supply, the PA delivers an output power of 750 muW with a maximum power-added efficiency (PAE) of 10%. The circuit also has a second output to test the effects of using an on-chip filter in low-power designs. This work demonstrates the feasibility of using class-E PAs for short-range, low-power applications

Random telegraph signal noise in CMOS active pixel sensors

We discuss the source of random telegraph signal (RTS) behavior in photodiodes, metal-oxide-semiconductor (MOS) transistors and active pixel sensors (APS). First, a detailed review on the magnitude and the time constants of RTS noise observed in state-of-the art small-pitch imagers will be presented. Second, the impact of RTS noise on the quality of the images obtained from MOS imagers will be discussed, with a focus on the noise requirements for biomedical imaging applications. Finally, our experimental results will be discussed and some ideas on how to deal with RTS noise in silicon imagers will be described based on the RTS noise analyses.