Murugappan Senthilvelan

Software implementation of WiMAX on the sandbridge sandblaster platform

This paper describes a Sandbridge Sandblaster system implementation including both hardware and software elements for a WiMAX 802.16e system. The system is implemented on the fully functional multithreaded Sandblaster multiprocessor SB3010 SoC chip. The entire communication protocol, physical layer and MAC, has been implemented in software using pure ANSI C programming language and it executes in real time. In this paper, we also present a radio propagation analysis specific to the Samos island at the workshop location, and the DSP execution performance.

Software Solutions for Converting a MIMO-OFDM Channel into Multiple SISO-OFDM Channels

We present a software approach for MIMO-OFDM wireless communication technology. We first show that complex matrix operations like singular-value decomposition (SVD), diagonalization, triangularization, etc., can be executed efficiently in software using a combination of CORDIC and unitary rotation algorithms in a multithreaded SIMD processor. We then investigate and analyze the transformation of a MIMO-OFDM channel into multiple independent SISO-OFDM channels by means of the SVD. The algorithms are implemented on the Sandblaster processor. The numerical results indicate that the CORDIC-augmented processor provides a significant reduction in the computing time of more than 47% over the standard sandblaster processor when converting a 4-by-4 MIMO-OFDM channel into four SISO-OFDM channels. The technique is applicable to emerging wireless communication protocols, such as WiMAX and Wi-Fi, and provides the flexibility required to adapt to continually changing and evolving standards without the need for expensive hardware redesigns and respins.

Analog Television, WiMAX and DVB-H on the Same SoC Platform

This paper presents a SW reconfigurable platform, capable of executing in real time both analog and digital television protocols as NTSC, PAL, SECAM and DVB-H. Our platform is also capable of executing WiMAX at 2.9 Mbps in real time, as well as other mobile telephony protocols like 3G UMTS or CDMA200. SW reconfigurability and low power consumption makes our platform suitable for mobile applications. Current analog and digital television systems have been developed in a combination of analog and/or digital hardware due to high computational processing requirements. They are also mostly limited to a single function either analog TV or, digital TV. DSPs in these systems have been limited to speech coding and orchestrating the custom hardware blocks. Despite the fact that in high-performance systems there may be over 2 million logic gates required to implement physical layer processing, the implementation may take many months to finalize. After the logic design is complete, any errors in the design may cause up to a 9 month delay in correcting and refabricating the device. This labor intensive process is counter productive to fast development cycles. In our approach, the entire physical layer is executed in SW using the SB3011 DSP from Sandbridge Technologies (Glossner et al., 2003) allowing fast development cycles and support of multiple functions

Instruction Set Extensions for Matrix Decompositions on Software Defined Radio Architectures

Emerging wireless applications consistently demand higher data rates. Unfortunately, it is challenging to achieve high data rates within the limited amount of available frequency spectrum. Hence, enhanced spectral efficiency and link reliability within the available frequency spectrum are of the utmost importance in current and next generation wireless protocols. To attain high spectral efficiency and link reliability, wireless protocols employ increasingly complex 2-dimensional techniques that involve computationally-intensive matrix operations. Multiple-Input Multiple-Output (MIMO) communication is an example of a promising technique employed by wireless protocols to deliver higher data rates at the cost of increased algorithmic complexity. Application Specific Integrated Circuits (ASICs) have traditionally been used to implement compute-intensive wireless protocols. The wireless industry has been gradually moving towards an alternative programmable platform called Software Defined Radio (SDR) due to its significant benefits, such as reduced development costs, and accelerated time-to-market. The computationally-intensive matrix operations used in current and next generation wireless protocols are extremely expensive to implement in SDR platforms with conventional Digital Signal Processor (DSP) instruction sets. Hence there is a need for novel instructions, hardware designs and algorithm enhancements to enable higher spectral efficiency on SDR platforms. In this paper, we propose Single Instruction Multiple Data (SIMD) CoOrdinate Rotation DIgital Computer (CORDIC) instruction set extensions with CORDIC hardware support to speedup computationally-intensive matrix decomposition algorithms. The CORDIC instruction set extensions have been implemented on the Sandbridge Sandblaster SB3000 SDR platform and evaluated on conventional algorithms used for decomposing a closed loop 4-by-4 Worldwide Interoperability for Microwave Access (WiMAX) MIMO channel into independent Single-Input Single-Output (SISO) channels. Our experimental results on the closed-loop MIMO channel decomposition using CORDIC instructions demonstrate more than 6x speedup over a Sandblaster baseline implementation that uses state-of-the-art SIMD DSP instructions. The CORDIC instructions also provide similar numerical accuracy when compared to the baseline implementation. The techniques we propose in this paper are also applicable to other SDR and embedded processor architectures.

Synchronization on heterogeneous multiprocessor systems

To meet the exponential increase in processing requirements of present day embedded system applications, System-On-Chip (SoC) designs increasingly have multiple processing elements on the same die. The functionality of these processing elements varies considerably, and includes hardware accelerators for specific Digital Signal Processing (DSP) kernels, high-performance DSP cores, and low-power application processors. While executing applications, these processing elements typically share system memory and peripherals, and hence need synchronization to maintain system integrity. Further complicating the issue is the fact that these processing elements can be custom designed or off-the-shelf Intellectual Property (IP) cores that are generally not designed for operation in multiprocessor environments, and consequently lack multiprocessor synchronization support. Hence there is a need for simple and elegant low-power, low-latency techniques for synchronization support that can be seamlessly integrated and require little or no modifications to the already pre-verified processing elements. In this paper, we describe synchronization counters, a mechanism that allows seamless implementation of low-latency multiprocessor synchronization with incremental hardware penalty. This mechanism is usable in heterogeneous multiprocessor environments even when the individual processing elements lack native synchronization support. The synchronization counters are implemented and verified on a four-processor SoC targeted for handheld devices, the Sandbridge Technologies SB3500. The SoC contains three special purpose DSPs and an ARM application processor, sharing system memory and peripherals.

Flexible arithmetic and logic unit for multimedia processing

Novel arithmetic units are needed to achieve the cost, performance, power, and functionality requirements of emerging multimedia systems. This paper presents the design and implementation of a 64-bit arithmetic and logic unit (ALU) for multimedia processing. The 64-bit ALU supports subword-parallel processing by allowing one 64-bit, two 32-bit, four 16-bit, or eight 8-bit operations to be performed in parallel. In addition to conventional ALU operations, the ALU also supports several operations for enhanced multimedia processing including parallel compare, parallel average, parallel minimum, parallel maximum, and parallel shift and add. To efficiently implement a variety of multimedia applications, the ALU supports saturating and wrap-around arithmetic operations on unsigned and twos complement operands. This paper compares the area and delay of the 64-bit multimedia ALU to those of a more conventional 64-bit ALU.

CORDIC instruction set extensions for matrix decompositions on Software Defined Radio processors

Software Defined Radio (SDR) is favored by the wireless industry as the platform of choice for implementing physical layers of wireless protocols due to its significant benefits of reduced development costs and accelerated time-to-market. However, to attain high spectral efficiency, emerging wireless protocols use increasingly complex two-dimensional techniques that are extremely expensive to implement using conventional Digital Signal Processor (DSP) instruction sets. In this paper, we present COordinate Rotation DIgital Computer (CORDIC) instruction set extensions that speed up the QR Decomposition (QRD) and Singular Value Decomposition (SVD) of complex matrices that are used in several important communication algorithms. The performance benefits are evaluated on the Sandbridge Sandblaster SB3000 low-power, multithreaded SDR processor. The proposed instructions provide significant performance improvements with little hardware overhead, while improving the accuracy of the wireless algorithms under investigation.

Automated generation of configurable media processors

Low-power media processors are important components in wireless multimedia cell phones, multimedia personal digital assistants, and other handheld multimedia devices. The ideal media processor implementation for these systems varies greatly based on cost, performance, and power requirements. This paper presents a design methodology for automatically generating synthesizable hardware description language (HDL) models for multimedia processors. The multimedia processors support the PLX instruction set architecture, and are configured based on a high-level machine definition file, which specifies the size of the processor datapath, the types of functional units, and the configuration for on-chip memory.

CORDIC-based LMMSE equalizer for Software Defined Radio

In Code Division Multiple Access (CDMA) systems, the orthogonality of the spreading codes used to achieve multiple access over a channel is severely degraded due to multi-path interference. Expensive equalization techniques are needed to recover the transmitted signal. The Linear Minimum Mean Square Error (LMMSE) equalizer is a sub-optimal equalizer that is a good compromise between computational complexity and communication system performance. It uses computationally-intensive matrix inversion operations to perform equalization. In this paper, we address the computational challenges of implementing the LMMSE equalizer on Software Defined Radio (SDR) platforms. SDR platforms are favored by the wireless industry due to their significant benefits of reduced development costs and accelerated time-to-market. We present COordinate Rotation DIgital Computer (CORDIC) Instruction Set Architecture (ISA) extensions that speed up the LMMSE equalization algorithm. The costs and benefits of the ISA extensions are evaluated on the Sandbridge Sandblaster 3000 (SB3000) low-power, multithreaded SDR processor. The proposed ISA extensions provide significant performance improvements with little hardware overhead, while improving the accuracy of the LMMSE Equalizer.