Mustafa H. Koroglu

A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs

This paper describes a 2.5-3.125-Gb/s quad transceiver with second-order analog delay-locked loop (DLL)-based clock and data recovery (CDR) circuits. A phase-locked loop (PLL) is shared between receive (RX) and transmit (TX) chains. On each RX channel, an amplifier with user-programmable input equalization precedes the CDR. Retimed data then goes to an 1:8/1:10 deserializer. On the TX side, parallel data is serialized into a high-speed bitstream with an 8:1/10:1 multiplexer. The serial data is introduced off-chip through a high-speed CML buffer having single-tap pre-emphasis. Proposed DLL-based CDR can tolerate large frequency offsets with no jitter tolerance degradation due to its second-order PLL-like nature. Also, this study introduces an improved charge-pump and an improved phase-interpolator. Fabricated in a 0.15-/spl mu/m CMOS process, the 1.9-mm/sup 2/ transceiver front-end operates from a single 1.2-V supply and consumes 65-mW/channel of which 32 mW is due to the CDR. CDR jitter generation and high-frequency jitter tolerance are 5.9 ps-rms and 0.5 UI, respectively, for 3.125 Gb/s, 2/sup 23/-1 PRBS input data with 800-ppm frequency offset.

A 2.5-3.125 Gb/s quad transceiver with second order analog DLL based CDRs

This paper describes a 2.5-3.125 Gb/s quad transceiver with second order analog DLL based clock and data recovery (CDR). The proposed CDR can tolerate large frequency offsets with no jitter tolerance degradation. Fabricated in a 0.15 /spl mu/m CMOS process, the 1.9 mm/sup 2/ transceiver front-end operates from a single 1.2 V supply and consumes 65 mW/channel of which 32 mW is due to the CDR. The CDR jitter generation and high-frequency jitter tolerance are 5.9 psec-rms and 0.5 UI, respectively, when a 3.125 Gb/s 2/sup 23/-1 PRBS data with 800 ppm frequency offset is applied.

A scalable architecture for fully integrated multi-TV tuners

Silicon TV tuners have recently achieved and surpassed bulky CAN tuners in terms of circuit performance, providing TV manufacturers lower-cost, smaller foot-print, and more reliable solutions. Silicon TV tuners also made packing multiple tuners into a single die or package possible. Multiple tuners are often needed for feature-rich TVs and Set-Top-Boxes with DVR, picture-in-picture and fast channel switching capabilities. Implemented in a 40nm CMOS technology, this paper presents major building blocks for a monolithic dual-tuner with active splitter, tracking filters and output buffers, a compact low-power VCO based ADC and a local oscillator generation scheme featuring a 17GHz VCO with fractional dividers.