Mustafa Parlak

Low power H.264 deblocking filter hardware implementations

In this paper, we present two efficient and low power H.264 deblocking filter (DBF) hardware implementations that can be used as part of an H.264 video encoder or decoder for portable applications. The first implementation (DBF_4times4) starts filtering the available edges as soon as a new 4times4 block is ready by using a novel edge filtering order to overlap the execution of DBF module with other modules in the H.264 encoder/decoder. Overlapping the execution of DBF hardware with the execution of the other modules in the H.264 encoder/decoder improves the performance of the H.264 encoder/decoder. The second implementation (DBF_16times16) starts filtering the available edges after a new 16times16 macroblock is ready. Both DBF hardware architectures are implemented in Verilog HDL and both implementations are synthesized to 0.18 mum UMC standard cell library. Both DBF implementations can work at 200 MHz and they can process 30 VGA (640times480) frames per second. DBF_4times4 and DBF_16times16 hardware implementations, excluding on-chip memories, are synthesized to 7.4 K and 5.3 K gates respectively. These gate counts are the lowest among the H.264 DBF hardware implementations presented in the literature. Our hardware implementations are more cost effective solutions for portable applications. DBF_16times16 has 36% less power consumption than DBF_4times4 on a Xilinx Virtex II FPGA on an Arm Versatile PB926EJ-S development board. Therefore, DBF_4times4 hardware can be used in an H.264 encoder or decoder for which the performance is more important, whereas DBF_16times16 hardware can be used in an H.264 encoder or decoder for which the power consumption is more important.

A novel computational complexity and power reduction technique for H.264 intra prediction

H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a novel technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware significantly without any PSNR and bitrate loss. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are equal, the prediction equations of H.264 intra prediction modes simplify significantly for this block. By exploiting the equality of the neighboring pixels, the proposed technique reduces the amount of computations performed by 4times4 luminance, 16times16 luminance, and 8times8 chrominance prediction modes up to 60%, 28%, and 68% respectively with a small comparison overhead. We also implemented an efficient 4times4 intra prediction hardware including the proposed technique using Verilog HDL. We quantified the impact of the proposed technique on the power consumption of this hardware on a Xilinx Virtex II FPGA using Xilinx XPower, and it reduced the power consumption of this hardware up to 18.6%.

Pixel similarity based computation and power reduction technique for H.264 intra prediction

H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a pixel similarity based technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware significantly. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are similar, the prediction equations of H.264 intra prediction modes are simplified for this block. The proposed technique reduces the amount of computations performed by 4×4 luminance, 16×16 luminance, and 8×8 chrominance prediction modes up to 68%, 39%, and 65% respectively with a small comparison overhead. The proposed technique does not change the PSNR for some video frames, it increases the PSNR slightly for some video frames and it decreases the PSNR slightly for some video frames. We also implemented an efficient 4×4 intra prediction hardware including the proposed technique using Verilog HDL. The proposed technique reduced the power consumption of this hardware up to 57%.

A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm

In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implemented using Verilog HDL. An AHB bus interface is designed and integrated into DBF hardware in order to communicate with ARM processor and SRAM through AHB bus. An efficient memory hierarchy and data transfer scheme is also implemented. The DBF hardware implementation works at 72 MHz in a Xilinx Virtex II FPGA and it can code 30 CIF frames (352times288) per second. The power consumption of DBF hardware is analyzed and up to 13% power savings is achieved by applying clock gating and glitch reduction techniques to DBF datapath.

An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter

This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. We use a novel edge filter ordering in a macroblock to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. The proposed architecture is implemented in VerilogHDL. The Verilog RTL code is verified to work at 72 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can code 30 GIF frames (352 times 288) per second

Computation and power reduction techniques for H.264 intra prediction

H.264 intra prediction algorithm has a very high computational complexity. In this paper, we propose pixel equality and pixel similarity based techniques for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware. These techniques exploit pixel equality and similarity in a video frame by performing a small number of comparisons among pixels used in prediction equations before the intra prediction process. If the pixels used in prediction equations are equal or similar, prediction equations simplify significantly. By exploiting the equality and similarity of the pixels used in prediction equations, the proposed pixel equality and pixel similarity based techniques reduce the amount of computations performed by 4x4 intra prediction modes up to 78% and 89%, respectively, with a small comparison overhead. We also implemented an efficient 4x4 intra prediction hardware including the proposed techniques using Verilog HDL. The proposed pixel equality and pixel similarity based techniques reduced the power consumption of this hardware up to 13.7% and 17.2%, respectively. The proposed pixel equality based technique does not affect the PSNR and bitrate. The proposed pixel similarity based technique increases the PSNR slightly for some videos frames and it decreases the PSNR slightly for some videos frames.

Energy reduction techniques for H.264 deblocking filter hardware

In this paper, we propose pixel equality and pixel similarity based techniques for reducing the amount of computations performed by H.264 Deblocking Filter (DBF) algorithm, and therefore reducing the energy consumption of H.264 DBF hardware. These techniques avoid unnecessary calculations in H.264 DBF algorithm by exploiting the equality and similarity of the pixels used in DBF equations. The proposed techniques reduce the amount of addition and shift operations performed by H.264 DBF algorithm up to 52% and 67% respectively with a small comparison overhead. The pixel equality based technique does not affect PSNR. The pixel similarity based technique does not affect the PSNR for some video frames, but it decreases the PSNR slightly for some video frames. We also implemented an efficient H.264 DBF hardware including the proposed techniques using Verilog HDL. The proposed pixel equality and pixel similarity based techniques reduced the energy consumption of this H.264 DBF hardware up to 35% and 39%, respectively. Therefore, they can be used in portable consumer electronics products that require real-time video compression.

Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra Prediction

H.264 intra prediction algorithm has a high computational complexity. This paper proposes a pixel similarity based technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are similar, the prediction equations of H.264 intra prediction modes are simplified for this block. The proposed technique reduces the amount of computations performed by 4x4 luminance prediction modes up to 68% with a small comparison overhead. This technique increases the PSNR slightly for some videos and it decreases the PSNR slightly for some videos. We also implemented an efficient 4x4 intra prediction hardware including the proposed technique using Verilog HDL. The proposed technique reduced the power consumption of this hardware up to 57%.

A Computation and Power Reduction Technique for H.264 Intra Prediction

H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a technique for reducing the amount of computations performed by H.264 intra prediction algorithm. For each intra prediction equation, the proposed technique compares the pixels used in this prediction equation. If the pixels used in a prediction equation are equal, this prediction equation is simplified significantly. By exploiting the equality of the pixels used in prediction equations, the proposed technique reduces the amount of computations performed by 4x4 luminance prediction modes up to 78% with a small comparison overhead. The proposed technique does not affect the PSNR and bit rate. We also implemented an efficient 4x4 intra prediction hardware including the proposed technique using Verilog HDL. We quantified the impact of the proposed technique on the power consumption of this hardware on a Xilinx Virtex II FPGA using Xilinx XPower, and it reduced the power consumption of this hardware up to 13.7%.

A novel energy reduction technique for H.264 intra mode decision

In this paper, we propose a novel energy reduction technique for H.264 intra mode decision. The proposed technique reduces the number of additions performed by Sum of Absolute Transformed Difference based 4×4, 16×16 and 8×8 intra mode decision algorithms used in H.264 joint model reference software encoder by 46%, 43% and 42% respectively for a CIF size frame without any PSNR loss. We also implemented an efficient H.264 16×16 intra mode decision hardware including the proposed technique using Verilog HDL. The proposed technique reduced the energy consumption of this H.264 16×16 intra mode decision hardware up to 59.6%.