Yusuf Adibelli

A novel computational complexity and power reduction technique for H.264 intra prediction

H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a novel technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware significantly without any PSNR and bitrate loss. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are equal, the prediction equations of H.264 intra prediction modes simplify significantly for this block. By exploiting the equality of the neighboring pixels, the proposed technique reduces the amount of computations performed by 4times4 luminance, 16times16 luminance, and 8times8 chrominance prediction modes up to 60%, 28%, and 68% respectively with a small comparison overhead. We also implemented an efficient 4times4 intra prediction hardware including the proposed technique using Verilog HDL. We quantified the impact of the proposed technique on the power consumption of this hardware on a Xilinx Virtex II FPGA using Xilinx XPower, and it reduced the power consumption of this hardware up to 18.6%.

A high performance and low energy intra prediction hardware for High Efficiency Video Coding

Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose novel techniques for reducing amount of computations performed by HEVC intra prediction algorithm, and therefore reducing energy consumption of HEVC intra prediction hardware. The proposed techniques significantly reduce the amount of computations performed by 4×4 and 8×8 angular prediction modes with a small comparison overhead without any PSNR and bit rate loss. We also designed and implemented a high performance HEVC intra prediction hardware for 4×4 and 8×8 angular prediction modes including the proposed techniques using Verilog HDL, and mapped it to a Xilinx Virtex 6 FPGA. The proposed techniques significantly reduce the energy consumption of the proposed hardware on this FPGA.

A high performance deblocking filter hardware for high efficiency video coding

The recently developed High Efficiency Video Coding (HEVC) international video compression standard uses adaptive deblocking filter for reducing blocking artifacts. Deblocking filters increase both subjective and objective quality. But, they have high computational complexity. Therefore, in this paper, the first HEVC deblocking filter hardware in the literature is proposed. Two parallel datapaths are used in the proposed hardware in order to increase its performance. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is verified to work correctly on an FPGA board. The proposed HEVC deblocking filter hardware can code 30 full HD (1920x1080) video frames per second. Therefore, it can be used in consumer electronics products that require a real-time HEVC encoder or decoder.

Pixel similarity based computation and power reduction technique for H.264 intra prediction

H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a pixel similarity based technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware significantly. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are similar, the prediction equations of H.264 intra prediction modes are simplified for this block. The proposed technique reduces the amount of computations performed by 4×4 luminance, 16×16 luminance, and 8×8 chrominance prediction modes up to 68%, 39%, and 65% respectively with a small comparison overhead. The proposed technique does not change the PSNR for some video frames, it increases the PSNR slightly for some video frames and it decreases the PSNR slightly for some video frames. We also implemented an efficient 4×4 intra prediction hardware including the proposed technique using Verilog HDL. The proposed technique reduced the power consumption of this hardware up to 57%.

A Reconfigurable HEVC sub-pixel interpolation hardware

Sub-pixel interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. Therefore, in this paper, a reconfigurable HEVC sub-pixel (half-pixel and quarter-pixel) interpolation hardware for all prediction unit sizes is proposed. The proposed reconfigurability reduces the area and power consumption of HEVC sub-pixel interpolation hardware more than 30%. The proposed hardware, in the worst case, can process 64 quad full HD (2560×1600) video frames per second.

A computation and energy reduction technique for HEVC intra mode decision

High Efficiency Video Coding (HEVC) intra mode decision algorithm has very high computational complexity. Therefore, in this paper, a computation and energy reduction technique is proposed for reducing the amount of computations performed by Sum of Absolute Transformed Difference (SATD) calculations in HEVC intra mode decision, and therefore reducing the energy consumption of HEVC SATD calculation hardware without any PSNR loss and bit rate increase. The proposed technique reduced the energy consumption of HEVC SATD calculation hardware up to 64.6%. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.

Computation and power reduction techniques for H.264 intra prediction

H.264 intra prediction algorithm has a very high computational complexity. In this paper, we propose pixel equality and pixel similarity based techniques for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware. These techniques exploit pixel equality and similarity in a video frame by performing a small number of comparisons among pixels used in prediction equations before the intra prediction process. If the pixels used in prediction equations are equal or similar, prediction equations simplify significantly. By exploiting the equality and similarity of the pixels used in prediction equations, the proposed pixel equality and pixel similarity based techniques reduce the amount of computations performed by 4x4 intra prediction modes up to 78% and 89%, respectively, with a small comparison overhead. We also implemented an efficient 4x4 intra prediction hardware including the proposed techniques using Verilog HDL. The proposed pixel equality and pixel similarity based techniques reduced the power consumption of this hardware up to 13.7% and 17.2%, respectively. The proposed pixel equality based technique does not affect the PSNR and bitrate. The proposed pixel similarity based technique increases the PSNR slightly for some videos frames and it decreases the PSNR slightly for some videos frames.

Energy reduction techniques for H.264 deblocking filter hardware

In this paper, we propose pixel equality and pixel similarity based techniques for reducing the amount of computations performed by H.264 Deblocking Filter (DBF) algorithm, and therefore reducing the energy consumption of H.264 DBF hardware. These techniques avoid unnecessary calculations in H.264 DBF algorithm by exploiting the equality and similarity of the pixels used in DBF equations. The proposed techniques reduce the amount of addition and shift operations performed by H.264 DBF algorithm up to 52% and 67% respectively with a small comparison overhead. The pixel equality based technique does not affect PSNR. The pixel similarity based technique does not affect the PSNR for some video frames, but it decreases the PSNR slightly for some video frames. We also implemented an efficient H.264 DBF hardware including the proposed techniques using Verilog HDL. The proposed pixel equality and pixel similarity based techniques reduced the energy consumption of this H.264 DBF hardware up to 35% and 39%, respectively. Therefore, they can be used in portable consumer electronics products that require real-time video compression.

A high performance deblocking filter hardware for High Efficiency Video Coding

The recently developed High Efficiency Video Coding (HEVC) international video compression standard uses adaptive deblocking filter for reducing blocking artifacts. Deblocking filters increase both subjective and objective quality. But, they have high computational complexity. In this paper, we propose the first HEVC deblocking filter hardware in the literature. Two parallel datapaths are used in the hardware to increase its performance. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is verified to work at 108 MHz in a Xilinx Virtex 6 FPGA. The proposed HEVC deblocking filter hardware can code 30 full HD (1920×1080) video frames per second. It can be used in an HEVC encoder or an HEVC decoder.

Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra Prediction

H.264 intra prediction algorithm has a high computational complexity. This paper proposes a pixel similarity based technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are similar, the prediction equations of H.264 intra prediction modes are simplified for this block. The proposed technique reduces the amount of computations performed by 4x4 luminance prediction modes up to 68% with a small comparison overhead. This technique increases the PSNR slightly for some videos and it decreases the PSNR slightly for some videos. We also implemented an efficient 4x4 intra prediction hardware including the proposed technique using Verilog HDL. The proposed technique reduced the power consumption of this hardware up to 57%.