Myeong-Hoon Oh

Design of asynchronous MSP430 microprocessor using balsa back-end retargeting

Balsa developed by Advanced Processor Technology(APT) Group of Manchester University presents robust design environment that supports both a framework for synthesizing asynchronous hardware systems and the language for describing such systems. In this paper, a design of microprocessor, MSP430, in balsa language and the functional verification of the controller is presented. Back-end retargeting is performed as a part of the design methodology in Balsa. By back-end retargeting procedure, a new technology library including FPGA cell library is incorporated into Balsa design environment. Moreover, the circuit area is analyzed and reduced in different implementation styles by replacing helpercells in balsa into standard cells of the target library.

Fine-grained power gating of datapath using FSM

As a fine-grained power gating method for achieving greater power savings, our approach takes advantage of the finite state machine with a datapath (FSMD) characteristic which shows sequential idleness among subcircuits. In an FSMD-based power gating, while only an active subcircuit is expected to be turned on, more subcircuits should be activated due to the power overhead. To reduce the number of missed opportunities for power savings, we deactivated some of the turned-on subcircuits by slowing the FSMD down and predicting its behavior. Our microprocessor experiments showed that the power savings are close to the upper bound.

472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device

In this paper, we design and analyze an asynchronous pipelined FIFO called a micropipeline with the awareness of “place & route” (P&R) on an FPGA device. We use a commercially available 65nm Virtex-5 devices and design a high-speed implementation of the asynchronous four-phase micropipeline with considering its layout on the device. The layout of our design is modified manually to meet timing constraints and to accelerate the speed of circuits. The asynchronous FIFO implemented on the Virtex-5 device shows 452MHz throughput and 648ps per-stage latency at the simulation under the worst case operating condition and around 472MHz throughput is observed at the actual measurement on a real working chip at room temperature.

Design of a clockless MSP430 core using mixed asynchronous design flow

There are various limitations on the supporting tools and design methodologies for the implementation of an asynchronous delay-insensitive model. In this paper, we propose a new design flow by exploiting a mixed model, which combines a bounded delay model and a delay-insensitive model. To develop the design flow, we use an asynchronous finite-state machine for the bounded delay model and the null convention logic for the delay-insensitive model. Further, we designed an MSP430 core to verify the proposed design flow and the results of simulation show that it exhibits a performance improvement of 30.34% over its synchronous counterpart.

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered 0.18 mm CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

A new data encoding scheme using multi-valued logic for an asynchronous handshake protocol

Conventional delay-insensitive (DI) data encoding mechanisms, such as dual-rail and 1-of-4 data encoding, suffer from increased wire costs and high power dissipation since 2N+1 physical wires are needed to transmit N-bit data. In this paper, a new data encoding scheme that uses multiple-valued logic (MVL) is proposed to reduce the number of wires needed, and this scheme is simulated and verified using Spice modeling.

Design of asynchronous 2-phase ternary encoding protocol using multiple-valued logic

Due to a half transitions for data transfers comparing with conventional 4-phase signalings, level-encoded dual-rail (LEDR) has been widely used in on-chip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers to maintain delay-insensitive encoding. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme, and the circuits are implemented using current-mode multiple-valued logics. In the simulation with 0.25 μm CMOS technology, the suggested circuits saves both latency and energy consumption over the wire length of 3 mm.

Low Static Powered Asynchronous Data Transfer for GALS System

For a globally asynchronous locally synchronous (GALS) system, data transfer mechanisms based on a current-mode multiple valued logic (CMMVL) has been studied to reduce complexity and power dissipation of wires. However, these schemes consume considerable amount of power even in idle states because of the static power caused by their inherent structure. In this paper, new encoder and decoder circuits using CMMVL are suggested to reduce the static power. The effectiveness of the proposed data transfer is validated by comparisons with the previous CMMVL scheme and conventional voltage-mode schemes such as dual-rail and 1-of-4 encodings through simulation with a 0.25-μm CMOS technology. Simulation results demonstrate that the proposed CMMVL scheme significantly reduces power consumption of the previous one and is superior to dual-rail and 1-of-4 schemes over wire length of 2 mm and 4 mm, respectively.