Myong-Hoon Roh

Fabrication and shear strength analysis of Sn-3.5Ag/Cu-filled TSV for 3D microelectronic packaging

In this study, lead free Sn-3.5Ag solder bumps have been deposited on Cu-filled through-silicon via (TSV) by electroplating method. The solder bumps are plated using an acidic solution composed of SnSO4, H2SO4, Ag2SO4, thiourea and an additive. The current density is varied from −30 to −60 mA/cm2 to obtain the eutectic Sn-3.5Ag solder. The copper is electroplated in TSV using an acidic solution of CuSO4·5H2O, H2SO4, HCl, and an inhibitor. The bottom-up Cu-filling in TSV is achieved by a 3-step pulse periodic reverse (PPR) electroplating. It has been observed that the eutectic Sn-3.5Ag solder is achieved at a current density of −55 mA/cm2. The solder bumps are further reflowed onto TSV at 260 °C for 20 seconds, and shear strength of the formed Sn-3.5Ag/Cu-filled TSV joint is investigated. The results indicate the formation of Cu6Sn5 and Ag3Sn intermetallic compounds (IMCs) at the joint interface. It is found that with an increase of shear speed from 0.5-10 mm/s, the shear stress initially increases to a maximum, and then decreases beyond shear speed of 10 mm/s through 500 mm/s. It is shown that the ductile fracture mode gradually decreases beyond shear speed of 10 mm/s and disappears completely at 500 mm/s.

Cu filling of TSV using various current forms for three‐dimensional packaging application

Purpose – The purpose of this paper is to overview the effect of electroplating current wave forms on Cu filling of through‐silicon‐vias (TSV) for three‐dimensional (3D) packaging.Design/methodology/approach – The paper takes the form of a literature review.Findings – Effective TSV technology for 3D packaging involves various processes such as via formation, filling with conductive material, wafer thinning, and chip stacking. Among these processes, high‐speed via filling without defect is very important for applying the TSV process to industry with a lower production cost. In this paper, the effects of various current forms on Cu electroplating of TSV such as direct current (DC), pulse current (PC), pulse reverse current (PRC), and periodic pulse reverse current (PPR) are described in detail including recent studies.Originality/value – TSV is a core technology for high density 3D packaging. This paper overviews the recent studies of various current forms on Cu‐filling of TSV.

Electroplating Characteristics of Sn–Bi Microbumps for Low-Temperature Soldering

In this paper, the characteristics of eutectic Sn-Bi microsolder bumps fabricated by electroplating are investigated. The underbump metallization (UBM) layers on a Si chip consist of Al, Cu, Ni, and Au, sequentially from bottom to top. The desired Sn-Bi bump size has a diameter of 22 μm and pitch of 44 μm. In order to obtain the optimal conditions for the eutectic Sn-Bi solder bumps, the polarization curves of Sn, Bi, and Sn-Bi electrolytes are analyzed, and the variation of the Sn- Bi composition as a function of the current density is measured. Experimentally, from the polarization curve, Bi and Sn start to deposit below -0.12 and -0.54 V, respectively, and Sn-Bi codeposition occurs below an electropotential of -0.54 V. The Bi content of the electroplated bumps decreases from 92.4 to 38.2 wt% when the current density is increased from 20 to 50 mA/cm2, and near-eutectic composition of the Sn-61 wt% Bi bump is obtained by plating at 40 mA/cm2 for 5 min. The surface of the Sn-Bi microsolder bumps show plate-like structures with acicular shapes, and the grain size increases with increasing current density. An intermetallic compound layer, estimated as AuSn4 with a thickness of about 0.5 μm, was observed between the UBM layers and the as-plated Sn-Bi bumps.

Various Cu Filling Methods of TSV for Three Dimensional Packaging

Through-silicon-via (TSV) is a major technology in microelectronics for three dimensional high density packaging. The 3-dimensional TSV technology is applied to CMOS sensors, MEMS, HB-LED modules, stacked memories, power and analog, SIP and so on which can be employed to car electronics. The copper electroplating is widely used in the TSV filling process. In this paper, the various Cu filling methods using the control of the plating process were described in detail including recent studies. Via filling behavior by each method was also introduced.

Cu Filling into TSV and Si Dice Stacking for 3 Dimension Packaging

최근 전자제품의 소형화, 다기능화의 요구가 증가함에 따라 고집적, 고밀도의 반도체 소자를 제조하기 위한 차세대 패키징 기술로서 TSV (Through Silicon Via)를 이용한 3차원 패키징 기술 연구가 활발히 진행되고 있다. TSV를 이용한 3차원 패키징 방법은 실리콘 웨이퍼를 관통하는 비아 (via) 홀에 전도성 금속을 충전시켜 칩 내부에 전기적 통로를 확보한 후 여러 개의 칩을 적층하여 실장하는 방법으로 실리콘 웨이퍼 내부에 모든 멀티칩 시스템을 형성할 수 있으며, 다른 멀티칩 모듈과 비교하여 높은 집적도를 가질 수 있는 기술이다. 또한, 칩간 연결에서 가장 단거리로 전기적 통전을 가능하기 때문에 신호전달감소와 전력소모를 최소화 할 수 있는 장점을 갖고 있다. (그림 1 참조

Microstructure and mechanical properties in hot-forged liquid-phase-sintered silicon carbide

Two kind of -SiC powders of different particle sizes ( and ), containing 7 wt% , 2 wt% and 1 wt% MgO as sintering additives, were prepared by hot pressing at for 1 h under applied pressures, and then were hot-forged at for 6 h under 40 MPa in argon. All the hot-pressed specimens consisted of equiaxed grains and were developed grain growth after hot-forging. The smaller starting powder was developed the finer microstructure. The microstructures on the surfaces parallel and perpendicular to the pressing direction of the hot-forged SiC were similar to each other, and no texture development was observed because of the lack of massive to phase transformation of SiC. The fracture toughness (), hardness (~ 25.2 GPa) and flexural strength (480 MPa) of hot-forged SiC using larger starting powder were higher than those of the other.

Texture Development in Liquid-Phase-Sintered β-SiC by Seeding with β-SiC Whiskers

Silicon carbide ceramics seeded with 10?30 wt% SiC whiskers are fabricated by hot pressing and annealing. A quantitative texture analysis including calculation of the Orientation Distribution Function (ODF) is used for obtaining the degrees of preferred orientation of the fabricated samples. The microstructure and crystallographic texture are discussed with respect to the effect of β-SiC whisker seeds on the resulting fracture toughness values. The SEM microstructures and the texture data reveal a correlation between texture and fracture toughness anisotropy.