Wonjoong Kim

Strength and fracture toughness of in situ-toughened silicon carbide

Fine β-SiC powders either pure or with the addition of 1 wt % of α-SiC particles acting as a seeding medium, were hot-pressed at 1800 °C for 1 h using Y2O3 and Al2O3 as sintering aids and were subsequently annealed at 1900 °C for 2, 4 and 8 h. During the subsequent heat treatment, the β → α phase transformation of SiC produced a microstructure of “in situ composites” as a result of the growth of elongated large α-SiC grains. The introduction of α-SiC seeds into the β-SiC accelerated the grain growth of elongated large grains during annealing which led to a coarser microstructure. The sample strength values decreased as the grain size and fracture toughness continued to increase beyond the level where clusters of grains act as fracture origins. The average strength of the in situ-toughened SiC materials was in the range of 468–667 MPa at room temperature and 476–592 MPa at 900 °C. Typical fracture toughness values of 8 h annealed materials were 6.0 MPa m1/2 for materials containing α-SiC seeds and 5.8 MPa m1/2 for pure β-SiC samples.

Preferred orientation of beta-phase and its mechanisms in a fine-grained silicon-nitride-based ceramic

A quantitative texture analysis, including calculations of the orientation distribution function, is applied to investigate the preferred orientation of β–Si 3 N 4 in a fine-grained material containing almost equiaxed grains that has been hot-pressed, annealed, and plane-strain compressed. The results show that (i) plane strain compression can produce relatively strong textures that were dependent on the compressive strain; (ii) the basal plane of hexagonal β–Si 3 N 4 was normal to the hot-pressing direction for the hot-pressed and annealed samples, whereas it was parallel to the stress axis for deformed samples; and (iii) the mechanisms for texture development were preferred grain growth for the annealed sample and grain rotation for the hot-pressed and deformed samples, respectively.

Cu filling of TSV using various current forms for three‐dimensional packaging application

Purpose – The purpose of this paper is to overview the effect of electroplating current wave forms on Cu filling of through‐silicon‐vias (TSV) for three‐dimensional (3D) packaging.Design/methodology/approach – The paper takes the form of a literature review.Findings – Effective TSV technology for 3D packaging involves various processes such as via formation, filling with conductive material, wafer thinning, and chip stacking. Among these processes, high‐speed via filling without defect is very important for applying the TSV process to industry with a lower production cost. In this paper, the effects of various current forms on Cu electroplating of TSV such as direct current (DC), pulse current (PC), pulse reverse current (PRC), and periodic pulse reverse current (PPR) are described in detail including recent studies.Originality/value – TSV is a core technology for high density 3D packaging. This paper overviews the recent studies of various current forms on Cu‐filling of TSV.

Cu Filling into TSV and non-PR Sn bumping for 3 Dimension Chip Packaging

. 성능 향상을 위해 평면적 칩 배열은 한정된 면적에 작은 칩을 여러 장 배열시키고, 칩의 개수가 증가함에 따라 칩을 서로 연결해주는 배선 길이가 증가하게 된다. 이로 인해 길어진 배선에서 신호 지연이 발생하여 칩 성능 향상에 대한 효과가 떨어지는 문제가 발생하게 된다. 이러한 한계점을 극복하기 위한 대안으로서 제기된 것이 TSV (Through Silicon Via) 기술을 이용한 3차원 칩 적층이다. TSV 기술은 실리콘 웨이퍼를 관통하는 미세 비아 (Via) 홀을 형성한 후 비아 홀 내부에 전도성 물질을 충전시켜 칩 내부에 직접 전기적 연결 통로를 확보하는 기술이다. 칩을 적층하여 패키징하는 3차원 패키징은 1개의 칩을 실장할 면적에 여러 개의 칩을 실장할 수 있어 집적도를 향상시킬 수 있으며, 전력 소모도 감소시킬 수 있는 장점이 있다. TSV를 이용한 칩 적층을 위해서는 실리콘 웨이퍼에 비아 홀을 제조하는 기술, 형성된 비아 홀에 기능 박막층을 형성하고 전도성 금속을 충전하는 기술, 실리콘 웨이퍼의 배면을 제거하여 충전된 비아 홀의 개구부를 노출시키는 CMP (Chemical Mechanical Polishing) 과정, 형성된 홀 표면에 범프를 형성하고 형성된 범프를 이용하여 칩을 적층하는 기술 등 복잡한 과정을 거쳐 완성된다 (그림 1 참조

Electroplating Characteristics of Sn–Bi Microbumps for Low-Temperature Soldering

In this paper, the characteristics of eutectic Sn-Bi microsolder bumps fabricated by electroplating are investigated. The underbump metallization (UBM) layers on a Si chip consist of Al, Cu, Ni, and Au, sequentially from bottom to top. The desired Sn-Bi bump size has a diameter of 22 μm and pitch of 44 μm. In order to obtain the optimal conditions for the eutectic Sn-Bi solder bumps, the polarization curves of Sn, Bi, and Sn-Bi electrolytes are analyzed, and the variation of the Sn- Bi composition as a function of the current density is measured. Experimentally, from the polarization curve, Bi and Sn start to deposit below -0.12 and -0.54 V, respectively, and Sn-Bi codeposition occurs below an electropotential of -0.54 V. The Bi content of the electroplated bumps decreases from 92.4 to 38.2 wt% when the current density is increased from 20 to 50 mA/cm2, and near-eutectic composition of the Sn-61 wt% Bi bump is obtained by plating at 40 mA/cm2 for 5 min. The surface of the Sn-Bi microsolder bumps show plate-like structures with acicular shapes, and the grain size increases with increasing current density. An intermetallic compound layer, estimated as AuSn4 with a thickness of about 0.5 μm, was observed between the UBM layers and the as-plated Sn-Bi bumps.

Non-PR Sn-3.5Ag Bumping on a Fast Filled Cu-Plug by PPR Current

The electroplating of Sn-3.5 wt% Ag bumps without a photoresist (PR) mould on a Si chip was performed to reduce the production steps and cost for 3-D chip stacking. The electroplating characteristics of Sn-Ag and Sn-Ag bump growth were examined. The Sn-Ag bumps were electroplated on the Cu-plugged TSVs (through-silicon vias) of a Si chip. The Cu plug in the via was produced using a high-speed Cu filling process by a periodic pulse reverse current waveform. The electroplating current was supplied to the exposed Cu surface in the TSVs to produce the Sn-3.5Ag bumps. As the experimental results show, the Sn-3.5Ag bumps were fabricated successfully without a PR mould, with no serious defects by electroplating. The Ag contents in the Sn-Ag bump decreased with increasing current density. Besides, the bump height and width increased with increasing plating time. The bump width grew isotropically because of the absence of a PR mould. The Sn-3.55 wt% Ag bumps were obtained at a current density of -55 mA/cm2 for 20 min on the Cu plugs.

Active Metal Brazing Applied to Joining of ZrO2-Ti Alloy

Abstract In this study, active metal brazing methods for ZrO 2 and Ti alloy were discussed. To get a successful metal-ceramic bonding, various factors (melting temperature, corrosion, sag resistance, thermal expansion coefficient etc. of base materilas and filler metal) should be considered. Moreover, in order to clarify bonding between the metal and ceramic, the mechanism of the interfacial structure of the joints should be identified. The driving force for the formation of metal and ceramic interfaces is the reduction of the free energy which occurs when their contact becomes complete. Interfacial bonding depends on the material combinations and the bonding processes. This study describes the bonding between ceramic and metal in an active metal brazing. Key Words : Vibration, Fatigue, Fracture, Intermetallic compound, Pb-free solder Fig. 1 Ceramic to metal seals products 3) 1. 서 론 금속과 세라믹의 접합기술은 전자전기 산업 관련하여 초소형 전자부품회로, 센서, MEMS, 고효율 열교환기, CERDIP pakage, 전자 패키징 등의 분야에 다양하게 응용되고 있다

Bonding Mechanism and Strength of Metals to Ceramics

Abstract Bonding technology and bonding mechanism of metal to ceramic including brazing, diffusion bonding, friction welding and etc were reviewed in this study. Various factors should be considered from a bonding design step to acquire a good bonding joint because of a large difference between metal and ceramic in crystal lattice, coefficient of thermal expansion and various properties. In addition, metal and ceramic bonding technologies are constantly being developed according to precise components, multi-function and application to harsh environment. However, improvement of bonding properties and bonding reliability also should be accompanied. Bonding of ceramics, such as ZrO 2 , Ti 3 AlC 2 and SiC, to metals like Ti-alloy, TiAl and steel were described in this paper.Key Words : Active metal brazing, Ceramics, Bonding mechanism, Wettability, Residual stress ISSN 1225-6153Online ISSN 2287-8955 1. 서 론 금속과 세라믹은 각종 물성에서 많은 차이점을 가지고 있기 때문에, 접합을 위해서는 재료에 관한 폭넓은 지식과 신뢰성 설계의 기초를 필요로 한다. 세라믹은 고온에서 뛰어난 내부식성, 내마모성을 갖고 있어서 산업 전반에 걸쳐 많이 이용되고 있다. 금속에 비해 세라믹은 고온에서 더 큰 강도를 갖고 더 낮은 열전도도 및 열팽창 계수를 가지지만, 세라믹이 가진 취성은 전기전자산업과 고온에서의 구조적 적용에 제한을 받는다. 따라서 세라믹의 응용범위를 확대하기 위해서는 금속과 함께 조합하여 사용하여야 한다. 그 예로서는 세라믹 코팅, 세라믹 섬유를 이용한 복합재료의 제조 및 금속-세라믹 접합 등이 있다. 최근 다양한 표면개질 기술을 사용하여 세라믹 표면의 접착력과 강도를 개선하는 연구들도 진행되고 있다

TSV Filling Technology using Cu Electrodeposition

Abstract TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addressesthe TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current densityon electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.Key Words : Through silicon via, 3D packating, Cu filling, Electrodeposition, Additive

Various Cu Filling Methods of TSV for Three Dimensional Packaging

Through-silicon-via (TSV) is a major technology in microelectronics for three dimensional high density packaging. The 3-dimensional TSV technology is applied to CMOS sensors, MEMS, HB-LED modules, stacked memories, power and analog, SIP and so on which can be employed to car electronics. The copper electroplating is widely used in the TSV filling process. In this paper, the various Cu filling methods using the control of the plating process were described in detail including recent studies. Via filling behavior by each method was also introduced.