Myoung Jin Lee

A Proposal on an Optimized Device Structure With Experimental Studies on Recent Devices for the DRAM Cell Transistor

We have experimentally analyzed the leakage mechanism and device degradations caused by the Fowler-Nordheim (F-N) and hot carrier stresses for the recently developed dynamic random-access memory cell transistors with deeply recessed channels. We have identified the important differences in the leakage mechanism between saddle fin (S-Fin) and recess channel array transistor (RCAT). These devices have their own respective structural benefits with regard to leakage current. Therefore, we suggest guidelines with respect to the optimal device structures such that they have the advantages of both S-Fin and RCAT structures. With these guidelines, we propose a new recess-FinFET structure that can be realized by feasible manufacturing process steps. The structure has the side-gate form only in the bottom channel region. This enhances the characteristics of the threshold voltage (VTH), ON/OFF currents, and the retention time distributions compared with the S-Fin structure introduced recently.

A Mechanism for Dependence of Refresh Time on Data Pattern in DRAM

We measured the refresh time (tREF) according to data patterns for several dynamic random access memory (DRAM) chips. The measured tREF depends on the cell data pattern; moreover, these have their own dependences, which differ for several DRAM chips. We analyzed these phenomena in terms of both refresh and offset measurements, and our novel result was that tREF dependence on data patterns is determined by both a cell leakage mechanism and an offset by sensing noise.

A New Direct Evaluation Method to Obtain the Data Retention Time Distribution of DRAM

The authors have developed an efficient and accurate method to obtain the data retention time distribution of DRAM from the physics-based device simulation and the numerical integration of the probability space composed of three independent random variables, namely 1) the number, 2) the location, and 3) the energy level of traps, where each trap acts as a localized leakage source. Compared with the recently proposed Monte Carlo method, this method is much more efficient and free from the statistical error in the tail distribution. Furthermore, it can be easily applied to the problem involving a complex geometry and the nonuniform spatial distribution of traps. With this method, the retention time distribution of an 80-nm technology DRAM with the recess-channel-array transistor is studied

Partial SOI type isolation for improvement of DRAM cell transistor characteristics

A new DRAM cell transistor using an isotropic etching under the storage node is proposed, and it is shown that the structure gives improvement both in the short-channel effect and in the body-bias control. The asymmetrical characteristics of the structure are analyzed by experiments and simulation, and the feasibility of utilizing the asymmetric characteristics is reported.

A Sensing Noise Compensation Bit Line Sense Amplifier for Low Voltage Applications

A new bit-line sense amplifier for improving performance in the presence of data-pattern-dependent sensing noise is analyzed. The proposed scheme utilizes the power drop phenomenon in the sense amplifier driving line, resulting in an 81.5% reduction in the amplitude of data-pattern-dependent sensing noise. It is very important to accurately model power drop in compensating data-pattern-dependent sensing noise. Simulation and measurement of the proposed sensing scheme show improvement of sensing noise over a conventional bit-line sense amplifier. Moreover, the type of sense amplifier driver circuit significantly affects the magnitude of the improvement. The impact of the sense amplifier driver layout is analyzed in order to better utilize the proposed scheme. Finally, an optimum data pattern noise insensitive sense amplifier and driver are proposed.

A bitline sense amplifier for offset compensation

The industry has continuously demanded lower voltages and higher densities in DRAM chips [1]. To satisfy this need, it is desirable to use a low VCORE in the DRAM core, even though with such a low voltage it is difficult to sense the cell signal due to an insufficient sensing margin in high density DRAM [2–3]. When the bitline (BL) sense amp (BLSA) starts the sensing operation, all the BLs in the cell array go to the data transition stage. This leads to sensing noise in the BLSA, resulting in a sensing failure. There are several noise sources that contribute to this sensing failure, but the major noise source is the coupling capacitance between the BL and the wordline (WL) [4], which leads to a cell MAT array noise as shown by the data patterns. We develop a BLSA to compensate for this MAT sensing noise. In this experiment, we fabricate a 68nm DRAM chip that shows only a 15% amplitude of the total normal chip noise by eliminating 85% of original MAT sensing noise by using a new BLSA scheme. Fabricated DRAM chips operate in the condition of VCORE = 1.5V and VDD = 1.8V. Generally, a sensing margin problem occurs in BLSAs with a large threshold voltage mismatch. Because this kind of worst-case BLSA is rare, we focus only on the worst BLSA found with a probability of 10−3%. All the measured data is from the BLSAs of 10−3% probability, which we define as a sensing margin failure.

Near-Infrared Detection Using Pulsed Tunneling Junction in Silicon Devices

We exploit the potential of the pulsed tunneling bias condition in silicon junctions (the Zener junction and the drain surface junction in nMOSFETs) to detect near-infrared (NIR) photon signals. A combination of the Franz-Keldysh effect and avalanche multiplication with minimization of the thermal effect through a pulsed tunneling bias is found to provide infrared radiation sensitivities as high as 1.18 and 0.89 A/W at the wavelengths of 1310 and 1550 nm, respectively, in a Zener diode. The potential of the drain surface junction in MOSFETs to function as an NIR sensor is also investigated using a similar bias scheme.

Physics-Based Simulation of 1/f Noise in MOSFETs under Large-Signal Operation

1/f noise in MOSFETs under large-signal excitation, which is important in CMOS analog and RF circuits, is modeled as a perturbation in the semiconductor equations employing the oxide-trapping model. The oxide-trapping model for a MOSFET in periodic large-signal operation shows that 1/f noise reduces more than the small-signal noise model predicts as the gate OFF voltage decreases further below the threshold voltage.

Reliability Studies on Non Planar DRAM Cell Transistor

We have experimentally analyzed the leakage mechanism and device degradations caused by the F-N and hot carrier stresses for the recently developed DRAM cell transistors having deeply recessed channels. We have found the important difference of the leakage mechanism between S-Fin and RCAT, which have each structural benefit in the characteristics of leakage current, so we can suggest the guide lines for device structures simultaneously having each merit in both structures.

Polysilicon near-infrared photodetector with performance comparable to crystalline silicon devices

We demonstrate high responsivity in a polysilicon (Poly-Si) near-infrared photodetector by reducing the adverse effects of grain boundaries. The presence of grain boundaries is a serious problem in polysilicon since they act as traps and degrade the electrical characteristics. However, the relation between grain boundaries and photodetector performance has not yet been reported. Here, the effect of grain boundary on the resistivity and responsivity of Poly-Si devices is investigated. The resistivity of Poly-Si is higher than that of crystalline Si (c-Si) at the same doping concentration due to the potential barrier of the grain boundary, and its degradation of electrical characteristics is mitigated here by increasing the doping concentration. The photodetector with a highly-doped polysilicon layer exhibits a responsivity of 0.48 A/W at 900 nm, which is almost the same as that of c-Si photodetectors. In contrast, polysilicon devices with the same doping concentration as c-Si devices show degraded responsivity due to grain boundary traps. In addition, to improve the responsivity at target wavelengths of 900 nm and 1,064 nm, we deposited an indium-tin-oxide layer, which reduces the surface reflectance on the Poly-Si photodetector. The responsivity is improved by 22.9% and 50.0% at 900 nm and 1,064 nm respectively compared to devices without the ITO. The results here confirm the ability to fabricate low cost Poly-Si photodetectors with high responsivity which show similar or superior optical response compared to commercial c-Si devices.