Chang-Ki Baek

A Proposal on an Optimized Device Structure With Experimental Studies on Recent Devices for the DRAM Cell Transistor

We have experimentally analyzed the leakage mechanism and device degradations caused by the Fowler-Nordheim (F-N) and hot carrier stresses for the recently developed dynamic random-access memory cell transistors with deeply recessed channels. We have identified the important differences in the leakage mechanism between saddle fin (S-Fin) and recess channel array transistor (RCAT). These devices have their own respective structural benefits with regard to leakage current. Therefore, we suggest guidelines with respect to the optimal device structures such that they have the advantages of both S-Fin and RCAT structures. With these guidelines, we propose a new recess-FinFET structure that can be realized by feasible manufacturing process steps. The structure has the side-gate form only in the bottom channel region. This enhances the characteristics of the threshold voltage (VTH), ON/OFF currents, and the retention time distributions compared with the S-Fin structure introduced recently.

High efficiency silicon solar cell based on asymmetric nanowire

Improving the efficiency of solar cells through novel materials and devices is critical to realize the full potential of solar energy to meet the growing worldwide energy demands. We present here a highly efficient radial p-n junction silicon solar cell using an asymmetric nanowire structure with a shorter bottom core diameter than at the top. A maximum short circuit current density of 27.5 mA/cm2 and an efficiency of 7.53% were realized without anti-reflection coating. Changing the silicon nanowire (SiNW) structure from conventional symmetric to asymmetric nature improves the efficiency due to increased short circuit current density. From numerical simulation and measurement of the optical characteristics, the total reflection on the sidewalls is seen to increase the light trapping path and charge carrier generation in the radial junction of the asymmetric SiNW, yielding high external quantum efficiency and short circuit current density. The proposed asymmetric structure has great potential to effectively improve the efficiency of the SiNW solar cells.

Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis

A compact scaling length model for tapered Tri-gate fin field-effect transistors (FinFETs) is presented based on a 3-D simulation and an analytic potential model. Short-channel effects (SCEs) of rectangular FinFETs can be controlled by designing the fin width, fin height, and gate length to satisfy scaling theory. Tapered FinFETs have a fin top width shorter than the fin bottom width, and they show a different dependence of subthreshold behaviors and SCEs compared to rectangular FinFETs. The proposed scaling length model for tapered FinFETs, expressed as a function of fin bottom width, fin height, and tapering angle, is presented based on the 3-D Poissons equation and a non-Cartesian mesh. The dependence of the subthreshold behaviors of tapered FinFETs calculated with the proposed model is compared with that of rectangular FinFETs. We found that longer fin bottom widths and fin heights of tapered FinFETs can be designed by applying the proposed scaling length model for the scaling parameter.

Characterization and Modeling of 1/

In this paper, the volume trap densities Nt are extracted from gate-all-around silicone-nanowire FETs with different gate oxides, using a cylindrical-coordinate-based flicker noise model developed. For extracting Nt, the drain-current power spectral densities were measured from a large number of identical devices and averaged over, thereby mimicking the spatial distribution of trap sites inducing 1/f curve. Also, effective mobility and threshold voltage were simultaneously extracted with the series resistance to characterize the 1/f noise in terms of intrinsic values of these two channel parameters. The volume trap densities thus extracted from different oxides (in situ steam-generated oxide/rapid thermal oxide/nitride-gated oxide) are compared and further examined using hot-carrier stress data. Finally, radius dependence of the cylindrical 1/f model developed is discussed.

f

The series resistance, R sd in silicon nanowire FETs (Si-NWFET) is extracted unambiguously, using the Y -function technique, in conjunction with the drain current and transconductance data. The volume channel inversion in Si-NWFET renders the charge carriers relatively free of the surface scattering and concomitant degradation of mobility. As a result, the Y -function of Si-NWFET is shown to exhibit a linear behavior in strong inversion, thereby enabling accurate extraction of R sd. The technique is applied to nanowire devices with channel lengths 82, 86, 96, 106, 132, and 164 nm, respectively. The extracted R sd values are shown nearly flat with respect to the gate voltage, as expected from Ohmic contacts but showed a large variation for all channel lengths examined. This indicates the process parameters involved in the formation of series contacts vary considerably from device to device. The present method only requires a single device for extraction of R sd and the iteration procedure for data fitting is fast and stable.

Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides

The photoresponse characteristics of In2Se3 nanowire photodetectors with the κ-phase and α-phase structures are investigated. The as-grown κ-phase In2Se3 nanowires by the vapor-liquid-solid technique are phase-transformed to the α-phase nanowires by thermal annealing. The photoresponse performances of the κ-phase and α-phase In2Se3 nanowire photodetectors are characterized over a wide range of wavelengths (300-900 nm). The phase of the nanowires is analyzed using a high-resolution transmission microscopy equipped with energy dispersive X-ray spectroscopy and X-ray diffraction. The electrical conductivity and photoresponse characteristics are significantly enhanced in the α-phase due to smaller bandgap structure compared to the κ-phase nanowires. The spectral responsivities of the α-phase devices are 200 times larger than those of the κ-phase devices. The superior performance of the thermally phase-transformed In2Se3 nanowire devices offers an avenue to develop highly sensitive photodetector applications.

Characteristics of the Series Resistance Extracted From Si Nanowire FETs Using the

The low-frequency noise in the silicon nanowire field-effect transistor (SNWFET) is characterized using SNWFETs with different channel diameters <i>d</i>_NW. The current density and the simulation result indicate that the volume inversion as manifested by the spatial charge distribution is enhanced in smaller <i>d</i>_NW. The measured noise data are discussed based on the number and correlated mobility fluctuation model. It is shown that the low-frequency noise decreases in smaller <i>d</i>_NW. This <i>d</i>_NW-dependent noise behavior is clarified in terms of the effective oxide trap density and the fraction of inversion charges near the Si-SiO₂ interface.

Y

In this paper, a simple but accurate model is presented to analyze source/drain (S/D) series resistance in trigate fin field-effect transistors, particularly on triangular or pentagonal rather than rectangular epitaxy. The model includes the contribution of spreading, sheet, and contact resistances. Although the spreading and sheet resistances are evaluated modifying standard models, the contact resistance is newly modeled using equivalent models of lossy transmission lines and transformations of 3-D to 2-D geometry. Compared with series resistance extracted from 3-D numerical simulations, the model shows excellent agreement, even when the S/D geometry, silicide contact resistivity, and S/D doping concentration are varied. We find that the series resistance is influenced more by contact surface area than by carrier path from the S/D extension to the silicide contact. To meet the series resistance targeted in the semiconductor roadmap, both materials and geometry will need to be optimized, i.e., lowering the silicide contact resistivity and keeping high doping concentration as well as maximizing the contact surface area, respectively.

-Function Technique

Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors.

Thermally Phase-Transformed In2Se3 Nanowires for Highly Sensitive Photodetectors

The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters