Myoungho Lim

Graded PZT thin film capacitors with stoichimetric variation by MOD technique

Abstract By tailoring Zr/Ti ratio in Pb(Zr,Ti)O3 from 45/55 to 75/25, functionally graded PZT thin films were prepared by metal organic decomposition (MOD) technique. P-E hysteresis loops were measured, and polarization was found to shift up or down depending on the direction of the composition gradients of the PZT. This polarization offset was modeled using Poissons equation in one dimension. Switching charge was also found to be compositional gradient direction dependent.

Electrical characteristics of PT-bismuth strontium tantalate(BST)-P-SI with zirconium oxide buffer layer

Abstract Electrical characteristics of Pt-BST-ZrO2-p-Si metal-ferroelectric-insulator-p Si (MFIS) structures have been investigated. The BST film was deposited by sol gel technique and annealed in oxygen environment for about an hour at 800°C. The capacitance-voltage characteristics of these structures show hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The hysteresis in the C-V characteristics were found to be dependent on the thickness of the buffer layer as well as on the duration of the applied voltage. A model based on the polarization of the ferroelectric film and charge injection at the silicon - insulator interface was proposed to explain the electrical characteristics.

Bond-quality characterization of silicon-glass anodic bonding

Abstract A simple testing method is presented that allows the comparison of the bond quality for anodically bonded wafers. An array of parallel metal lines of predetermined thickness is formed on a glass wafer. The estimation of the bond quality can be performed by visual inspection after the bonding. This method enables comparison of the anodic-bonding process performance for different glasses, for intermediate layers and various bonding conditions. The optimization of silicon-glass anodic bonding with an intermediate phosphosilicate glass (PSG) layer is shown using this technique.

High density and long retention non-destructive readout FeRAM using a linked cell architecture

Abstract A 64 Kbit non-destructive readout (NDRO) ferroelectric random access memory (FeRAM) using a 0.6-μm technology is described. The NDRO FeRAM uses a novel linked cell architecture, which minimizes the circuit overhead accepted in Flash memories. This test device has shown 10-year retention and unlimited read operation. An 120-ns NDRO operation is performed at a read voltage of 2.2V. Circuit techniques used in the NDRO FeRAM include: (1) direct programming of ferroelectric capacitors, (2) automatic restoring of read data, and (3) data storing under zero bias conditions. The unique linked cell architecture allows for scaling a cell size down to 6F 2, where F is the minimum feature size available.

The future of ferroelectric memories

Since 1984, ferroelectric RAMs (FeRAMs) have been demonstrated in many applications such as smart cards and low-density memories. Prior to 1984, attempts failed because of the poor quality of thin films of complex materials. Currently, two materials compete for the large-scale integration development of FeRAMs. The first is a perovskite ceramic known as PZT (PbZr/sub 1-x/Ti/sub x/O/sub 3/). The second material is known as a layered perovskite such as SBT (SrBi/sub 2/Ta/sub 2/O/sub 9/). For low-density devices which employ thin films of either material with a thickness <300 nm operated at 3-5 V, both materials yield approximately the same results. As FeRAMs enter the deep submicron realm, the ferroelectric thin-film technology is ready to support high-density integration. SBT-based devices can be integrated as capacitors in DRAM-like 1T/1C stacked cells and flash-like FeFET cells. Experience with embedded FeRAMs is positive, so that the system-on-chip as well as stand-alone high-density devices are foreseen. The possibility of 1 V operation at a few to several tens of nanoseconds write with nonvolatility brings FeRAMs to the forefront of non-volatile memories. Scaling of capacitor areas as small as 0.04 /spl mu/m/sup 2/ is possible. With capacitor and FET technologies, FeRAMs blur the line between non-volatile memories as DRAM-like destructive read-out (DRO) devices and flash-like non-destructive read-out (NDRO) devices, which compete for the highly mobile generation of Internet devices and G-3 phones.

The role of buffer layer in strontium bismuth tantalate based ferroelectric gate mos structures for non-volatile non destructive read out memory applications

Abstract Metal Ferroelectric Insulator Semiconductor (MFIS) structure has been fabricated with strontium bismuth tantalate (SBT) as the ferroelectric thin film and zirconium oxide (ZrO2) as the insulating buffer layer. SBT film was deposited by spin-on metal organic deposition (MOD) technique. ZrO2 film was deposited by electron beam evaporation. The capacitance versus voltage characteristics(C-V) of the MFIS structure shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The C-V characteristics of MFIS structure shows memory window of 1.8 volts for a write/erase voltage of 9V at a sweep rate of 1 sec/1.8V. In order to understand the role of coercive voltage on the memory window in MFIS structures, C-V characteristics metal-ferroelectric-metal (MFM) structures with various SBT film thickness’ were also studied.

Advanced simulation tool for FeRAM design

Abstract A ferroelectric capacitor model was derived, and a ferroelectric device library was implemented into SPICE (both PSPICE and HSPICE) simulation tool. With this SPICE model, 1T-1C/2T-2C, or any other ferroelectric circuit, such as FeFET, chain cell, link cell can be simulated accurately and in real-time. Simulations of hysteresis loops, TVS, switching characteristics are shown in this paper.

SBT-based ferroelectric FET for nonvolatile non-destructive read out (NDRO) memory applications

Abstract SrBi2Ta2O9 based Ferroelectric FETs with a CeO2 buffer layer deposited by Metal Organic Decomposition (MOD) were fabricated on p-Si (100) substrate and analyzed in detail. The hysterisis curve (drain current vs. gate voltage) of the FET shows the counter-clockwise direction, which demonstrates the change of channel conductivity due to the ferroelectric polarization. The memory window with the gate voltage of ±10V was 2V. The difference of current ratio of Ids(on) to Ids(off) was 5∼7 orders in magnitude which is easily sensed by sense amplifiers. The charges of “on” state stored decay logarithmically with time without severe initial loss of data. This indicates the FET-FeRAM can be implemented in NDRO applications.

A read-disturb-free ferroelectric gate fet memory

Abstract The enhancement-type ferroelectric gate field-effect transistor (FeFET) requires a read biasing voltage to the gate to secure a sufficient on/off current ratio. However, disturb (depolarization) of the ferroelectric by repetitive applications of read biasing voltage to the gate is a potential reliability concern. This paper deals with the disturb issue for an experimentally fabricated FeFET with a stacked gate comprised of metal/SrBi2Ta2O9/CeO2. A significant difference between a high ON current and a low OFF current is brought about and sustained after a large number of read operations by choosing a proper gate voltage, which is not only enough to make a positively programmed FeFET turn on, but also effective to prevent the disturb effect.

Asymetric C-V characteristics of graded PZT thin film capacitors

Abstract Functionally graded PZT thin films were deposited via MOD technique by varying Zr/Ti ratio in Pb(Zr,Ti)O3. Large signal C-V and small signal C-V were measured by using Symetrix Tester. They are found to be asymmetric compared to that of non-graded PZT capacitors and were gradient direction dependent. Its proposed that the built in potential due to graded polarization is the cause of the asymmetry.