T. Otsuki

A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns

One of the most important features for ferroelectric material is fast write at low voltage. This feature is used in a 256 kb nonvolatile memory that operates at 3 V power supply with a read/write time of 100 ns. Active current is 3 mA at 200 ns cycle time at 3 V for battery operation. The cell consists of 1 transistor and 1 capacitor per bit (1T1C) permitting a high level of integration. For low-voltage low-power operation, use is made of a preset reference-cell circuit, wordline boost circuits with a ferroelectric boosting capacitor and a divided-cell plate circuit.<<ETX>>

Integration technology of ferroelectrics and the performance of the integrated ferroelectrics

Abstract We have successfully incorporated the ferroelectric and the high dielectric constant capacitors into integrated circuits. The GaAs MMICs with BST capacitors have been widely used for cellular phones. The BST technology is also applied to a silicon CCD delayline processor for VCRs and camcorders. With respect to the ferroelectric technology with Y1, an experimentally fabricated 256k bit FeRAM has exhibited the remarkable performance of the 100 ns and 3V operation with a 1T/1C cell configuration dedicated for the FeRAM. These integrated ferroelectrics have been achieved by controlling the ferroelectric properties in thin films and incorporating the films into GaAs and silicon devices with outstanding process technology. Furthermore, we refer to the memory cell design technology which enables the FeRAM to work below 1V. Various advantages of low-voltage and high-speed operation inherent in integrated ferroelectrics will be emphasized on the intelligent microelectronics applications toward the next m...

Low temperature crystallization of SrBi2Ta2O9 (SBT) films

Abstract 650°C process of SrBi2Ta2O9 (SBT) has been achieved through the use of new metal organic deposition (MOD) solution and the optimization of the deposition conditions. The sample showed a high remnant polarization (2Pr) of 14 μC/cm2 @3V, a low leakage current of 10–8 A/cm2 or less @3V, and a fatigue-free nature. We believe this processing will realize high-density FeRAM integration of SBT.

Highly-reliable ferroelectric memory technology with bismuth-layer structured thin films (Y-1 family)

A highly-reliable ferroelectric memory (FeRAM) which ensures retention of data written at a low voltage of 2.5 V and humidity resistance for 10 years under a high temperature of 70/spl deg/C has been successfully developed for the first time. These excellent characteristics have been attained by a newly developed ferroelectric material with mixed superlattice crystal of Y-1 family and a integration technology which makes the use of pl-SiN passivation possible.

Low temperature crystallization of mocvd deposited sbt films

Abstract An annealing 650°C process for SrBi2Ta2O9 (SBT) has been achieved in metal organic chemical vapor deposition (MOCVD). An optimized post anneal step at 650°C is also included. The samples showed a high remnant polarization (2Pr) of 14 μC/cm2 @5V, low leakage current of 10−8 A/cm2 or less @4V, and a fatigue-free nature. This is the first report of MOCVD deposited SBT that can achieve 650°C crystallization with the post annealing.

High density and long retention non-destructive readout FeRAM using a linked cell architecture

Abstract A 64 Kbit non-destructive readout (NDRO) ferroelectric random access memory (FeRAM) using a 0.6-μm technology is described. The NDRO FeRAM uses a novel linked cell architecture, which minimizes the circuit overhead accepted in Flash memories. This test device has shown 10-year retention and unlimited read operation. An 120-ns NDRO operation is performed at a read voltage of 2.2V. Circuit techniques used in the NDRO FeRAM include: (1) direct programming of ferroelectric capacitors, (2) automatic restoring of read data, and (3) data storing under zero bias conditions. The unique linked cell architecture allows for scaling a cell size down to 6F 2, where F is the minimum feature size available.

The future of ferroelectric memories

Since 1984, ferroelectric RAMs (FeRAMs) have been demonstrated in many applications such as smart cards and low-density memories. Prior to 1984, attempts failed because of the poor quality of thin films of complex materials. Currently, two materials compete for the large-scale integration development of FeRAMs. The first is a perovskite ceramic known as PZT (PbZr/sub 1-x/Ti/sub x/O/sub 3/). The second material is known as a layered perovskite such as SBT (SrBi/sub 2/Ta/sub 2/O/sub 9/). For low-density devices which employ thin films of either material with a thickness <300 nm operated at 3-5 V, both materials yield approximately the same results. As FeRAMs enter the deep submicron realm, the ferroelectric thin-film technology is ready to support high-density integration. SBT-based devices can be integrated as capacitors in DRAM-like 1T/1C stacked cells and flash-like FeFET cells. Experience with embedded FeRAMs is positive, so that the system-on-chip as well as stand-alone high-density devices are foreseen. The possibility of 1 V operation at a few to several tens of nanoseconds write with nonvolatility brings FeRAMs to the forefront of non-volatile memories. Scaling of capacitor areas as small as 0.04 /spl mu/m/sup 2/ is possible. With capacitor and FET technologies, FeRAMs blur the line between non-volatile memories as DRAM-like destructive read-out (DRO) devices and flash-like non-destructive read-out (NDRO) devices, which compete for the highly mobile generation of Internet devices and G-3 phones.

Gigabit-scale DRAM capacitor technology with high dielectric constant thin films by a novel conformal deposition technique

High dielectric constant Ba/sub 0.7/Sr/sub 0.3/TiO/sub 3/ (BST) thin films with excellent thickness uniformity, within 5%, and adequate structural properties across an 8 inch wafer, are prepared by a novel aerosol-driven and photo-enhanced conformal deposition technique. Storage capacitors fabricated with an ultrathin BST film which has the lowest equivalent SiO/sub 2/ thickness of 0.37 nm reported thus far, show that leakage current density is 2/spl times/10/sup -8/ A/cm/sup 2/ under an applied voltage of 2 V and unit capacitance is 95 fFspl mu/m/sup 2/. Combining these material properties with the proposed conformal deposition technique which is applicable for stacked cell structures, is very promising as key technologies for the future gigabit-scale DRAMs.<<ETX>>

Microstructure-induced Schottky barrier effects in barium strontium titanate (BST) thin films for 16 and 64 Mbit (DRAM cells)

The current-voltage and capacitance-voltage characteristics of fine-grained, ceramic BST thin films for ULSI (ultralarge-scale integrated) DRAM (dynamic random-access memory) applications are examined. A model and pertinent data for integrated BST capacitors used in 16/64-Mb DRAM cells are presented. The results confirm in detail the conclusion of R. Waser and M. Klee (1991, 1992) that conduction in ceramic SrTiO/sub 3/ is Schottky-dominated and that the Schottky barriers arise from depletion regions at grain boundaries and not only at the ferroelectric/electrode interface.<<ETX>>

Advanced LSI embedded with FeRAM for contactless IC cards and its manufacturing technology

Abstract High performance LSIs embedded with ferroelectric random access memory (FeRAM) for contactless IC cards are now commercially available. The emphasis is placed on the materials solution with SrBi2(Ta,Nb)2O9 (SBTN) which enables to exploit the potential performance of FeRAMs for composite logic/microcontroller LSIs operating at high speeds and low powers. The leading-edge 0.6-μm and double-level-metal FeRAM technology produces microcontroller-embedded LSIs with 14-kbit or 64-kbit FeRAM. A mature 0.8-μm and single-level-metal process has been built to maximize the die yield. Yields exceeding 90% indicate the excellent process stability. Product qualification data have proven the robust FeRAM technologies.