Myron Buer

Single-Event Charge Collection and Upset in 40-nm Dual- and Triple-Well Bulk CMOS SRAMs

CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the ion-induced single-event response between these two technology options, however, are not well understood. This paper presents a comparative analysis of heavy ion-induced upsets in dual-well and triple-well 40-nm CMOS SRAMs. Primary factors affecting the charge-collection mechanisms for a wide range of particle energies are investigated, showing that triple-well technologies are more vulnerable to low-LET particles, while dual-well technologies are more vulnerable to high-LET particles. For the triple-well technology, charge confinement and multiple-transistor charge collection triggers the “Single Event Upset Reversal” mechanism that reduces sensitivity at higher LETs.

Contribution of Control Logic Upsets and Multi-Node Charge Collection to Flip-Flop SEU Cross-Section in 40-nm CMOS

Heavy-ion measurements on 40-nm flip-flops indicate pattern dependence of cross-section resulting from local control logic upsets, such as clock nodes. A Monte-Carlo model of the flip-flop, calibrated to the heavy-ion data, is used to analyze the impact of multi-node charge collection within a flip-flop due to a single particle strike. Depending on the nodes that collect charge, multi-node charge collection can either increase or decrease the vulnerability of the cell. For neutrons, the overall effect of such events was found to be a net increase in cross-section by up to 16%.

Effects of charge confinement and angular strikes in 40 nm dual- and triple-well bulk CMOS SRAMs

Heavy-ion induced upsets are compared in dual-well and triple-well 40 nm CMOS SRAMs. Charge confinement in triple-well structures triggers the single-event upset reversal mechanism for high LET particles. Due to upset reversal, high LET ion-hits incident at off-normal angles show a decrease in SER compared to normally-incident ions for triple-well SRAM cells.

Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories

On-chip process monitor/sensor circuits capture the process corner of a chip in the postfabrication stage. Logic-NMOS and logic-PMOS based sensors, however, fail to capture the process corners for memories, as bitcells have a different implant from logic cells. In this paper, a novel on-chip bitcell-based process monitor (BPMON) circuit is implemented that distinguishes between and detects the standard global corner of memories in any chip. It leverages a current-mirror and a near-threshold biased bitcell array structure that changes the output voltage of the circuit in accordance with changes in the process corner. BPMON separately tracks bitcell NMOS and bitcell PMOS process corners. Silicon data from over 100 chips from five wafers in 28 nm CMOS shows correct bitcell process corner predictions. These predictions show the expected strong correlation with read and write vccmin, enabling vccmin to be lowered below specifications while still achieving a 100% yield.