Myunghwan Ryu

Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

Performance and power analysis of through silicon via based 3D IC integration

In the recent decades, power consumption of System on Chip (SoC) is getting more dominant and Through-Silicon Via (TSV) technology has emerged as a promising solution to enhance system integration at lower cost and reduce footprint. Powerful microprocessor and immense memory capability integrated in standard 2D IC enabled to improve IC performance by shrinking IC dimensions. Our research evaluates the impact of Through-Silicon Via (TSV) on 3D chip performance as well as power consumption and investigates to understand the optimum TSV dimension (i.e., diameter, height, etc...) for 3D IC fabrication. The key idea is using the physical and electrical modeling of TSV which considers the coupling effects as well as TSV-to-bulk silicon parameters in 3D circuitry. In addition, by combining the conventional metrics for planar IC technology with TSV modeling, several methodologies are developed to evaluate the 3D chips behavior with respect to interconnect and repeaters. For example, by exploiting 101-stage Ring Oscillator and 100-inverter chain into 3D IC, it can be said that the through silicon via brings substantial benefits on local interconnect layers by improving overall transmission speed and reducing power consumption. The results in our research show that by adopting TSV infusion we can both reduce the power dissipation of interconnect and improve overall performance up to 35% in 4-die stacking case. Like all ICs, the TSV based 3D stacked IC need to be analyzed for manufacturing process variation. Hence, we investigate the variation of TSV dimension and then propose the optimal shape of TSV for the best performance of 3D systems integration. From simultaneous Monte Carlo simulations of TSV height and diameter, we can conclude that for given specific pitch in 3D IC technology, TSV with a small diameter is best for 3D IC performance and energy dissipation.

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

Increasing short channel effects (SCEs) hinder further technology downscaling of CMOS transistors. Beyond the 10-nm technology node, the gate-all-around (GAA) FET is considered a promising solution for continuing Moore’s law. In this study, we introduce a novel structure for speeding up the interconnect propagation using 10-nm channel length double gate-all around (DGAA) transistors. We propose a boosting structure that can significantly improve the performance of circuits by controlling the two gates of the DGAA independently. The proposed structure demonstrates that the propagation delay can be reduced by up to 30% for short interconnects and 47% for long interconnects. In high-speed, low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between power consumption and performance, which will play an important role in application-specific integration circuits in future GAAbased designs.

Analysis of structural variation and threshold voltage modulation in 10-nm double gate-all-around (DGAA) transistor

Increasing short channel effects (SCE) interrupt the further technology scaling in the CMOS transistors. Beyond 10 nm technology node, the gate-all-around (GAA) FET is considered as a promising solution for continuing the Moores law. In this paper, we report the analysis of the double gate-all-around (DGAA) FET in terms of structural variations and the effect of the threshold voltage modulation by independently controlled inner gate. The impact of inner gate thickness and gate oxide thickness variations on the electrical characteristic of the DGAA FET are investigated. In addition, we propose the inner gate utilization to modulate the threshold voltage of the transistor for providing more design options.

Diffusion-rounded CMOS for improving both Ion and Ioff characteristics

This paper presents a simple and optimized device layout developed by using diffusion rounding effect for better electrical behavior of transistors. TCAD analysis shows that diffusion rounding at the transistor source side can provide increased Ion with decreased Ioff because of the edge effect. The proposed diffusion-rounded CMOS shows as much as 10% improvement in the on-current (driving) and the off-current (leakage) is saved up to 10%. The inverter layout shows that proposed method requires less than a 4% cell area increase for the same driving strength of original cells.

Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel width

We investigate the electrical characteristics of a double-gate-all-around (DGAA) transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET) with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over th...

Sandwiched-gate inverter: Novel device structure for future logic gates

In this paper, we propose a novel sandwiched-gate inverter by using of an NMOS GAA together with a donut-type PMOS. The DC operation and the transient performance of the proposed inverter were investigated with 3D TCAD simulations. The proposed inverter exhibits a correct inverter operation with a high noise margin and speed.

Transistor Layout Optimization for Leakage Saving

In this paper, we investigate electrical effects of transistor layout shape (both in the channel and diffusion) on the performance and leakage current. Through layout optimization techniques, we propose a novel intra-gate biasing technique to reduce leakage current while maintaining drive current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits. Diffusion rounding is another interesting effect which happens due to the imperfect source and drain profile in the sub-wavelength lithography regime. TCAD analysis shows that diffusion rounding at the transistor source side can provide increased Ion with decreased Ioff because of the edge effect. The proposed diffusion-rounded CMOS shows as much as 10% improvement both in the on-current (driving) and the off-current (leakage).

Simple and accurate capacitance modeling of 32nm multi-fin FinFET

In this paper, we investigate capacitive effect of multi-fins FinFET using the TCAD simulations. The analysis of the capacitance change is performed for the fin pitch and height variation in 32nm single gate FinFET. The analysis results show, as expected, that the increasing fin pitch (Pfin) variation leads to decrease in the coupling capacitance. And increasing height of the fin (Hfin) leads to increase in the capacitive coupling and total gate capacitances. Simple and accurate coupling capacitance models for both pitch and height variations of the three fins FinFET are proposed and verified with TCAD results.

A high resolution and high linearity 45nm CMOS fully digital voltage sensor for low power applications

This paper proposes a design of voltage sensor with new controllable delay element (CDE) having high linearity and high resolution. The proposed CDE uses power supply node to measure the voltage value. However, the delay increases exponentially at low voltage level. In this paper we add a PMOS header in parallel with the conventional CDE to compensate the delay degradation at lower voltage. We develop a 16-levels fully digital voltage sensor with a voltage range of 0.8 ∼ 1.1V and 20mV resolution by using of the proposed delay elements. The proposed circuit is designed and simulated in a 45 nm CMOS process. The simulation results show the feasibility of the high resolution and high linearity at low voltage by using of the proposed delay elements.