Youngmin Kim

Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

Building a laboratory surveillance system via a wireless sensor network

Contemporary technical experimentations become complicated. Therefore, a smart laboratory environment is needed for effective laboratory activities. In particular, a monitoring/surveillance system is needed to detect and regulate extreme ambient conditions in the laboratory. In this paper, we describe how a thermal comfort laboratory surveillance system is constructed via the deployment of a wireless sensor network (WSN). In order to prolong system lifetime as well as improve system reliability, a habit-based adaptive sensing mechanism has been proposed. Evaluations of on-site deployment results indicate the functionality and feasibility of the proposed WSN.

Performance and power analysis of through silicon via based 3D IC integration

In the recent decades, power consumption of System on Chip (SoC) is getting more dominant and Through-Silicon Via (TSV) technology has emerged as a promising solution to enhance system integration at lower cost and reduce footprint. Powerful microprocessor and immense memory capability integrated in standard 2D IC enabled to improve IC performance by shrinking IC dimensions. Our research evaluates the impact of Through-Silicon Via (TSV) on 3D chip performance as well as power consumption and investigates to understand the optimum TSV dimension (i.e., diameter, height, etc...) for 3D IC fabrication. The key idea is using the physical and electrical modeling of TSV which considers the coupling effects as well as TSV-to-bulk silicon parameters in 3D circuitry. In addition, by combining the conventional metrics for planar IC technology with TSV modeling, several methodologies are developed to evaluate the 3D chips behavior with respect to interconnect and repeaters. For example, by exploiting 101-stage Ring Oscillator and 100-inverter chain into 3D IC, it can be said that the through silicon via brings substantial benefits on local interconnect layers by improving overall transmission speed and reducing power consumption. The results in our research show that by adopting TSV infusion we can both reduce the power dissipation of interconnect and improve overall performance up to 35% in 4-die stacking case. Like all ICs, the TSV based 3D stacked IC need to be analyzed for manufacturing process variation. Hence, we investigate the variation of TSV dimension and then propose the optimal shape of TSV for the best performance of 3D systems integration. From simultaneous Monte Carlo simulations of TSV height and diameter, we can conclude that for given specific pitch in 3D IC technology, TSV with a small diameter is best for 3D IC performance and energy dissipation.

Energy-efficient hybrid adder design by using inexact lower bits adder

Approximation in the adder logic is a promising solution for energy-efficient designs in various applications. In this study, new hybrid adder design, which consists of an accurate adder for higher bits and proposed approximate adders for lower bits, is investigated. The XOR-based inexact adder is modified to be used in the approximation part. Simulation results of 16-bits adders show that error rates can be reduced significantly by the proposed hybrid adder compared to other approximation adders with smaller number of transistors than an accurate adder.

GIDL simulation and optimization for 0.13 /spl mu/m/1.5 V low power CMOS transistor design

In this work, we calibrate a BTBT model based on measured GIDL data, and incorporate the model into our process/device simulations to directly correlate process with device performance and leakage. For the first time, we quantitatively explore an overall picture of tradeoffs between device leakage and performance as functions of process conditions. The explored design space has been used in process optimization for our 0.13 /spl mu/m/1.5 V low power (LP) CMOS transistors. We demonstrate that such predictive TCAD simulations to determine and optimize process conditions can effectively reduce development time and cost. We describe GIDL mechanisms in our 0.13 /spl mu/m/1.5 V LP transistors, and explain, via simulations, that the measured GIDL current manifests different IN behaviors depending on whether the dominant BTBT location is at the gate oxide/Si interface or below in the Si bulk.

Adaptive approximate adder (A 3 ) to reduce error distance for image processor

Approximate computing is a solution for energy-efficient designs providing trade-off between accuracy and power. Especially vision-related processors are suitable applications to use approximation. So both error distance and error rate, which are important for output quality, are essential metrics in approximate computing logics. In this study, we propose an adaptive approximate adder by using of a modified XNOR-based adder with an adaptive method to configure the approximation bits during runtime. Simulation results of 16-bits adders show that both error distance and error rate are significantly improved by the proposed adder compared to other approximation adders.

Novel adaptive power gating strategy of TSV-based multi-layer 3D IC

Among power dissipation components, the leakage power has become more dominant with each successive technology node. A power gating technique has been widely used to reduce the standby leakage energy. In this work, we investigate the power gating strategy of TSV-based 3D IC stacking structures. Power gating control is becoming more complicated as more dies are stacked. We combine the on-chip PDN and TSV in a multilayered 3D IC for a power gating analysis of the static and dynamic voltage drops and in-rush current. Then, we propose a novel power gating strategy that optimizes the inrush current profile, subject to the voltage-drop constraints. Our power gating strategy provides a minimal wake-up latency such that the voltage noise safety margins are not violated. In addition, the layer dependency of the 3D IC on the power gating in terms of the wake-up time reduction is analyzed. We achieve an average wake-up time reduction of 28% for all cases with our adaptive power gating method that exploits location (or layer) information of the aggressors in a 3D IC.

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

Increasing short channel effects (SCEs) hinder further technology downscaling of CMOS transistors. Beyond the 10-nm technology node, the gate-all-around (GAA) FET is considered a promising solution for continuing Moore’s law. In this study, we introduce a novel structure for speeding up the interconnect propagation using 10-nm channel length double gate-all around (DGAA) transistors. We propose a boosting structure that can significantly improve the performance of circuits by controlling the two gates of the DGAA independently. The proposed structure demonstrates that the propagation delay can be reduced by up to 30% for short interconnects and 47% for long interconnects. In high-speed, low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between power consumption and performance, which will play an important role in application-specific integration circuits in future GAAbased designs.

A Wide-Range On-Chip Leakage Sensor Using a Current–Frequency Converting Technique in 65-nm Technology Node

As technology moves toward the submicrometer regime, leakage current due to aggressive scaling and parameter variation has become a major problem in high-performance integrated circuit designs. Therefore, accurate measurement of the leakage current flowing through transistors has become a critical task for better understanding of process and design. In this brief, we propose a simple on-chip circuit technique for measuring a wide-range static standby (or leakage) current in a 65-nm technology with high accuracy. The circuit consists of a current amplifier, a bias stabilizer, and a voltage-controlled oscillator. The proposed leakage sensor is designed to measure leakage currents from 20 pA to 20 nA. Simulation results show that the proposed sensor has less than 8.4% error over a wide range of leakage currents (i.e., three orders of magnitude). Chip measurement results also indicate that the proposed leakage sensor is operating properly and measures the standby leakage current values of the devices under test within the possible range at different temperatures. The power consumption of the proposed leakage sensor was 0.6 mW when the leakage current was 1 nA, and the active area was 0.007 mm 2.

Analysis of structural variation and threshold voltage modulation in 10-nm double gate-all-around (DGAA) transistor

Increasing short channel effects (SCE) interrupt the further technology scaling in the CMOS transistors. Beyond 10 nm technology node, the gate-all-around (GAA) FET is considered as a promising solution for continuing the Moores law. In this paper, we report the analysis of the double gate-all-around (DGAA) FET in terms of structural variations and the effect of the threshold voltage modulation by independently controlled inner gate. The impact of inner gate thickness and gate oxide thickness variations on the electrical characteristic of the DGAA FET are investigated. In addition, we propose the inner gate utilization to modulate the threshold voltage of the transistor for providing more design options.