N. Hashizume

Monte Carlo simulation of AlGaAs/GaAs heterojunction bipolar transistors

A first demonstration of one-dimensional Monte Carlo simulations of AlGaAs/GaAs heterojunction bipolar transistors is reported. The electron motion is solved by a particle model, while the hole motion is solved by a conventional hydrodynamic model. It is shown that the compositional grading of AlxGa1-xAs in the base region is effective to cause the ballistic acceleration of electrons in the base region, resulting in a high collector current density of above 1 mA/µm2. The current-gain cutoff frequency fT reaches 150 GHz if the size of a transistor is properly designed. Also shown is the relation between the device performances and the electron dynamics investigated.

Principles of operation of short-channel gallium arsenide field-effect transistor determined by Monte Carlo method

The electrical properties of a GaAs FET having a practical doping density and having a quarter-micrometer source-drain distance and a quarter-micrometer gate length have been studied by two-dimensional Monte Carlo particle simulation.I_{ds} = 3.3mA/20µm,g_{m} = 600mS/mm, andf_{T} = 160GHz are predicted. The reasons for the high performances are discussed in terms of the electron dynamics in the device. The current saturation mechanism and the current control mechanism of the FET are made clear.

Complementary GaAs SIS FET inverter using selective crystal regrowth technique by MBE

A first complementary GaAs semiconductor-insulator-semiconductor (SIS) FET inverter has been fabricated by constructing n-channel and p-channel GaAs SIS FETs on a single LEC GaAs substrate using MBE selective crystal regrowth technique. The fabricated inverter shows an inverter operation as a really low-power complementary inverter.

GaAs inversion-base bipolar transistor (GaAs IBT)

A completely new type of GaAs bipolar transistor with a base formed by a two-dimensional hole gas has been fabricated. The transistor has no metallurgical base layer but has an extremely thin inversion hole layer working as a base layer. The current gain β = 5.6 at 77 K and β = 17.1 at 300 K was obtained for the common emitter mode.

Study of an Elevated Drain Fabrication Method for Ultra-Shallow Junction

An elevated diffusion layer fabricated from polycrystalline silicon (poly-Si) by solid phase diffusion was investigated in detail by secondary-ion mass spectroscopy (SIMS) analysis. We clarified that it was necessary to control the native oxide in the poly-Si/Si substrate interface and use small-grained poly-Si to fabricate uniform and controllable shallow junctions. The low-capacitance sidewall-elevated drain (LCSED) metal oxide semiconductor field-effect transistor (MOSFET) fabricated by the oxygen-free load-lock low-pressure chemical vapor deposition (LPCVD) poly-Si (L/L poly-Si) was extremely effective for marked scaling down of transistor size and realizing an ultra low reversed junction leakage current.

Submicron-Length Tungsten-Gate Self-Aligned GaAs FET

A first submicron-gate ion-implanted self-aligned GaAs FET that has ever been made is reported. The FET has a 0.5 µm-long, 0.24 µm-thick tungsten gate which was fabricated by lift-off process and subsequently served as a mask for n+-implantation. The self-aligned FET showed the transconductance 2.4 times as large as that of a conventional FET of the same dimensions. The source-gate breakdown voltage was in excess of –3 V.

Schottky-contact coupling between Schottky-electrode-triggered Gunn elements

Signal transmissions between Schottky-electrode-triggered Gunn elements are investigated when an output electrode, also of Schottky type, is directly coupled to a trigger electrode of the next stage. Expressions are derived that describe the voltages across the two Schottky barriers when the barriers behave as pure capacitances. Also cases are studied where a conductive current flows through either of the barriers. In those cases, it is pointed out that excess electrons accumulate on the metal sides of the barriers after a cycle of potential changes at the semiconductor sides Experimental results agree well with those predicted by the present theory, and it is shown that the electron-accumulation phenomenon really takes place. Also a Gunn-effect memory device based on the above electron-accumulation phenomenon is proposed and demonstrated.

Two-Dimensional Electron Gas in an n+-GaAs/Undoped AlGaAs/Undoped GaAs SIS Structure

The two-dimensionality of the electronic system in a new self-aligned GaAs MIS-like FET having an n+-GaAs/undoped AlGaAs/undoped GaAs SIS structure is demonstrated by the angular dependent characteristics of SdH effects. The mobility of two-dimensional electron gas in a GaAs-SISFET is shown to be 120000 cm2/Vs with a sheet carrier concentration of 6.6×1011 cm-2 at 4.2 K and VG=0.6 V. The quantized Hall effect is realized by changing gate voltages at as low a magnetic field as 3.5 T.

Experimental study of the control characteristics of a Schottky-trigger electrode on a Gunn device

To clarify the condition for the generation of a high-field domain in a Gunn device equipped with a Schottky-trigger electrode, a detailed experimental study was carried out. The difficulties in such experiments had so far rested in the accurate evaluation of the potential difference between the trigger electrode and the semiconductor thereunder, which we solved by an equivalent circuit representation of the device. Moreover, the accuracy of the evaluation of the potential difference was further increased by making use of the critical condition for the forward current through the Schottky barrier of the trigger electrode. From the experimental results it was made clear that a high-field domain is not necessarily generated when the field in the channel under the trigger electrode reaches the threshold field, but some form of the over-threshold-field state is established before a domain is generated. This shows that the device could be biased to higher anode voltages, leading to higher output voltages and wider operational margines than had earlier been expected.

Erratum: Speed-power property of GaAs Schottky-barrier coupled Schottky-barrier gate FET logic

Results from computer simulation of a GaAs Schottky-barrier coupled Schottky-barrier gate FET logic inverter of different values of Vp are reported. It is shown that the inverter of gate dimensions 1 × 10 ?m?2, Vp = ?1 V, and fan-out of one has tpd = 17 ps and P = 1 mW, and that still lower power consumption is possible with smaller |Vp|. Problems associated with small |Vp| are also discussed.