Kazutaka Tomizawa

Breakdown-speed considerations in InP/InGaAs single- and double-heterostructure bipolar transistors

The breakdown and speed characteristics of InP/InGaAs single and double HBTs are presented. Temperature-dependent two- and three-terminal measurements suggest that avalanche impact ionization is the dominant breakdown mechanism in InGaAs collector HBTs. Monte Carlo techniques and 1D drift-diffusion modeling are used for speed and breakdown simulation, respectively. Special doping profiles are evaluated for improving the breakdown-speed characteristics of single HBTs (SHBTs) with conventional uniformly doped InGaAs collectors. Double HBTs (DHBTs) outperform all SHBTs in terms of speed-breakdown tradeoffs as long as they use graded base-collector junctions or they operate under sufficiently high collector-emitter voltage conditions. A cutoff frequency of 200 GHz was found to be feasible with graded DHBTs, and breakdown voltages up to 4.6 V were evaluated with a 3000-AA-thick collector. Nongraded DHBTs can be optimized to perform better in terms of speed-breakdown tradeoffs provided that a high collector doping is used. >

Principles of operation of short-channel gallium arsenide field-effect transistor determined by Monte Carlo method

The electrical properties of a GaAs FET having a practical doping density and having a quarter-micrometer source-drain distance and a quarter-micrometer gate length have been studied by two-dimensional Monte Carlo particle simulation.I_{ds} = 3.3mA/20µm,g_{m} = 600mS/mm, andf_{T} = 160GHz are predicted. The reasons for the high performances are discussed in terms of the electron dynamics in the device. The current saturation mechanism and the current control mechanism of the FET are made clear.

Monte Carlo studies of the effect of emitter junction grading on the electron transport in InAlAs/InGaAs heterojunction bipolar transistors

InAlAs/InGaAs HBTs with various emitter junction gradings are simulated using a self-consistent Monte Carlo simulator. The effects of the emitter junction grading and the shift of the emitter-base p-n junction into the emitter depletion region due to diffusion of the base dopant are investigated. A minimum transit time of 1.18 ps is predicted for an In(Ga/sub 1-x/Al/sub x/)As grading with x=0.6 at the E-B interface and J/sub C/=0.7*10/sup 5/ A/cm/sup 2/. Graded-base designs do not offer any transit time performance improvement compared with the graded E-B approach. For transient performance, the device switching time is found to remain constant at about 2.2 ps up to x/sub 0/ approximately 0.7 but increases for larger values. A cutoff frequency as high as 270 GHz was observed for x/sub 0/=0.7, indicating that the best transport can be achieved from intermediately graded rather than abrupt E-B junction designs. >

Ensemble Monte Carlo simulation of an AlGaAs/GaAs heterostructure MIS-like FET

An ensemble Monte Carlo simulation of a heterostructure MIS-like FET is presented in which the quasi-two-dimensionality of electron gas in the heterostructure is taken into account by the lowest three subbands. An AlGaAs/GaAs heterostructure MIS-like FET with a 1- mu m-long gate has been investigated. The electron transport is discussed, as well as the dependence of device performance on the gate length and on the thickness of the AlGaAs semi-insulating layers. The electronic potential in the channel of the FET is substantially affected by the equipotential of the gate metal, showing a nonuniform high electric field present in the submicrometer channel. The electronic transport in the FET reflects this nonuniform high electric field, resulting in nonstationary and hot-electron transport in the submicrometer channel. >

Fabrication technology of ultrafine SiO2 masks and Si nanowires using oxidation of vertical sidewalls of a poly-Si layer

A fabrication technology of the vertical ultrafine SiO2 wall masks using oxidation of sidewalls of a polycrystalline silicon (poly-Si) layer and Si nanowires utilizing the SiO2 wall masks have been developed. To obtain the vertical SiO2 wall mask, an optimum electron cyclotron resonance (ECR) plasma etching and a suitable wet etching of the poly-Si layer after the sidewall oxidation has been achieved. The vertical ultrafine SiO2 wall masks 10 nm wide and 90 nm high with 33 nm in space have been successfully fabricated for the first time. The dimensions of width and space become essentially smaller than the size of an electron beam resist pattern. The height is sufficient for ECR plasma etching. Si nanowires 10 nm wide and 18 nm thick have been precisely obtained by the ECR plasma etching of the thinned silicon-on-insulator layer using the vertical ultrafine SiO2 wall masks. The fabrication technology using the vertical ultrafine SiO2 wall masks has remarkable merits of fineness, scalability, and wide appl...

Fabrication technology of a Si nanowire memory transistor using an inorganic electron beam resist process

We report on a novel fabrication technology of a Si nanowire memory transistor using an inorganic SiO2 electron beam (EB) resist process. The inorganic EB resist process technique was put to practical use in Si nanodevice fabrication for the first time. We have successfully demonstrated the 15-nm-wide and 20-nm-thick Si nanowire memory transistor with a Si nanodot less than 10 nm in diameter. In the fabricated Si nanowire nanodot memory transistor, we have observed a large electron memory effect, i.e., a threshold voltage shift ΔVth of 2.2 V at room temperature. It is experimentally shown that the inorganic EB resist process is promising for fabricating various Si nanodevices.

Breakdown-speed considerations in AlGaAs/GaAs heterojunction bipolar transistors with special collector designs

The breakdown-speed tradeoffs of AlGaAs/GaAs HBTs with special collector designs are presented. Monte Carlo techniques and 1-D drift-diffusion modeling are used for speed and breakdown simulation, respectively. Base current reversal is indicative of breakdown and is used in conjunction with the (breakdown voltage/total transit time) figure of merit in order to set up HBT performance criteria. Conventional (n/sup -/) and inverted field (p/sup -/) collectors show a good speed-breakdown compromise over a limited collector current density. Equally good characteristics but over a broader current range can be obtained from collector launcher ( delta n/sup +/-n/sup -/- delta p/sup +/) HBTs. Undoped collector HBTs (i- delta p/sup +/) operate best at low currents. Overall, the use of special collector structures does not always guarantee the best speed-breakdown performance. >

Analysis of backscattering phenomenon from drain region in a silicon nanodiode

In this paper, the backscattering phenomenon from drain region in a silicon nanodiode was analyzed. A Monte Carlo simulation is employed for analyzing the backscattering effect in a short channel device.

Phonon scatterings of quasi two-dimensional electron gas in a single heterostructure

The wave functions and energy levels of quasi two-dimensional electron gas in a single heterostructure are evaluated by a variational technique. The scattering rates of quasi two-dimensional electron gas due to the acoustic, non-polar optical and polar optical phonons are calculated by using the wave functions thus obtained.

Backscattered electrons from a drain region in a silicon decanano diode

We have systematically and quantitatively studied the properties and effect of the backscattered electrons from the drain region of a silicon (Si) decanano diode in order to investigate the backscattering effect on the characteristics of a Si decanano device. An ensemble Monte Carlo (EMC) simulation is employed, in which the scattering effect with backscattered electrons from the drain region is taken into account. The results of the numerical experiment revealed the following remarkable conclusion. The density ratio of the backscattered electrons to all electrons in the channel becomes large when the channel length is as short as or less than 20 nm. The average position of the backscattered electrons normalized by the channel length moves closer towards the source side as the channel length becomes short. The backscattering effect on the drain current strongly depends on the channel length rather than the drain voltage. When the channel length is more than 40 nm, the backscattered electrons do not affect the drain current at all. The backscattering effect on the drain current is more enhanced when the channel length is as short as or less than 40 nm and when the drain voltage is also small. Furthermore, a design guide for avoiding the effect of backscattering on the drain current is presented for the first time. We believe that it becomes more important to analyze the backscattering phenomenon from the drain region along with the miniaturization of the decanano device.