N. Luke Seed

A single chip video signal processing architecture for image processing, coding, and computer vision

A new VLSI (CMOS) architecture for an internally multiprocessing, single chip, SIMD-based video signal processor (VSP) is presented. The limitations of extended DSP architectures and conventional array processors are discussed in the context of image processing, coding and computer vision. How this gives rise to the architecture is described. Architectural flexibility is provided by the integration of a novel array-based processing core, together with a RISC processor, intelligent memory interface processor, and internal cache RAM. The array core architecture is a second generation, enhanced array whose key features are: 2 b datapath, dual processor mesh-connected array planes and combined SIMD/systolic functionality. The core is optimized for 2-D windowed operations, particularly 2-D multiply-accumulation and transforms. The device is expected to operate at 80 MHz on low voltage silicon and deliver real-time performance across a range of target applications. >

Benchmarking of Bootstrap Temporal Stereo using Statistical and Physical Scene Modelling

Temporal stereo vision algorithms can offer improved robustness, however, this can only be delivered after several frames of a stereo image sequence have been processed. We present a new method of bootstrapping temporal stereo which can overcome such start-up problems by applying additional coarse-to-fine pre-processing to the first few images in a stereo sequence. To gauge the performance of temporal bootstrapping, we have employed a new algorithmic evaluation technique that uses statistical and physical scene modelling to produce accurate result errors data. The performance of the bootstrap temporal stereo algorithm, as determined by the automatic evaluation technique, as well the results from real stereo image sequences, are presented.

A photolithographic process for grossly non-planar substrates

We describe a technique whereby photolithography has been extended to the patterning of near micron-scale features onto grossly non-planar substrates. Examples will be given of track widths down to ten microns patterned over surfaces with vertical dimensions in excess of one centimetre - far outside the normal bounds of photolithography. The technique enables many novel microsystem packaging schemes and provides an alternative to the direct-write methods that are traditionally employed for patterning non-planar surfaces. The technique is based on the computation of the phase/amplitude distribution on the mask that, when illuminated with light of sufficient spatial coherence, will recreate the desired non-planar light distribution. This has some similarities to existing RET and inverse lithography techniques, but is extended to grossly non-planar surfaces. Exposure of an electrophoretic photoresist-coated substrate to the light field created by the mask enables the non-planar pattern to be transferred to the substrate. The holographic mask contains localized Fresnel patterns. We discuss the analytical methods used for their computation, the approximations necessary to enable mask manufacture and the effects of these approximations on image quality. We also discuss more general numerical methods of mask computation.

A generalized computer vision chip

Abstract This paper describes a generalized video convolution processor (VCP) which fulfils the requirements of an algorithm for depth estimation from stereo image pairs allowing the acceleration of this process to near-real-time rates. In particular, the VCP is designed to perform high-precision image rectification. The very high level of mathematical integrity which is required for this operation is not supported by commercial image warping devices. Additionally, the generality of the processor allows it to be used across a wider range of computer vision and image processing applications. A prototype has been fabricated using a two-layer metal 1 μm CMOS process and the chip operates at 30 MHz. The VCP can rectify a 256 × 256 image at 25 frames/sec and allows truly arbitrary image warps.

Holographic Lithography on Vertical Surfaces

Holograms of 3D images are combined with noise suppression and off-axis projection to image arbitrary patterns onto a vertically oriented plane. This has important applications in microfabrication, for instance writing on the edges of silicon chips.