N. Masmoudi

Electronic control in electric vehicle based on CAN network

Bus-multiplexed structure of electronic systems in electric vehicle has many advantages. The most important is the connective reduction (size and length of wires) that reduces the electromagnetic interference, which is agreed with EMC (electromagnetic compatibility). In addition, only two wires are required to manage a different system, which necessitates an exchange of date between them. This can only done by networking, using a controller area network (CAN) bus. After a brief introduction of the need for the CAN network in embedded system particularly in electric vehicle application, we describe necessary acquired data in electric vehicle system. Then we present the new developed unit band on CAN network, for date control and acquisition in different levels: conception, structure and links with other systems.

Design and chip implementation of modified CORDIC algorithm for Sine and Cosine functions application: PARK transformation

The CO-ordinate Rotation DIgital computer (CO.R.DI.C) algorithm is an iterative procedure to evaluate various elementary functions. In this contribution, design and chip implementation of modified CORDIC algorithm for sine and cosine are presented. Modified CORDIC algorithm reduce the number of iterations. The modified algorithm needs, at most, half the number of iterations to achieve the same accuracy as the classical algorithm. The modifications are applicable to circular CORDIC in rotation modes. The hardware integration is carried out using field programmable gate arrays (F.P.G.As). To demonstrate the performances of the design, pipeline architecture of the CORDIC algorithm is studied. The design is used to compute the PARK transformation in control theory for electric vehicle.

An efficient hardware architecture design for H.264/AVC INTRA 4×4 algorithm

In this work, we present architecture for real-time implementation of INTRA 4X4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4times4 is composed by intra prediction 4times4, integer transform 4times4, quantization 4times4, inverse integer transform 4times4, inverse quantization 4times4. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 160 MHz in an ALTERA Stratix II FPGA. This architecture can process one macroblock (MB) for 432 clock cycles.

Electronic implementation of a neural observer in FPGA technology application to the control of electric vehicle

This paper presents a new integration approach for the control of an induction machine in the FPGA technology. The proposal is based on the design of an adaptive observer that makes it possible to generate the induction machine parameters in real time. The proposed observer is based on the use of neural networks whose their generalisation capacity allows the compensation of the induction machine parameter variations. Considering the enormous algorithmic resources requested by the neural network integration, an optimised architecture of the observer is proposed using CORDIC algorithm. It makes it possible to show the best performances in time and area on the technology SPARTAN of XILINX.

Complexity analysis of intra prediction in H.264/AVC

In this paper, we study the computational complexity of the intra prediction module for video coding software according to H.264/AVC standard. We analyze separately the complexity of each intra mode for the implementation on TMS320C64 platform. The intra prediction unit consists of predicting the blocks pixels from their neighbors according to different directional modes (horizontal, vertical, ...) and others non-directional (DC, planar). For each mode, we compute the number of the executional sub-units (add, shift, load, store...). Together with the number of necessary cycles to execute every instruction and the functional units that can perform these instructions, we can deduce the complexity of every intra mode. To estimate the total complexity of the intra prediction process, we assume that the encoder tests all intra modes. The total cycles account is estimated by multiplying the number of cycles of each mode by the number of blocks in the picture. Our results indicate that our methodology for the complexity analyses of the intra prediction unit of the H.264/AVC provides a good approximation with respect to the experimental results.

An Efficient Hardware Architecture Design for H.264/AVC INTRA 4X4 Algorithm

In this work, we present architecture for real-time implementation of INTRA 4 times 4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4 times 4 is composed by intra prediction 4 times 4, integer transform 4 times 4, quantization 4 times 4, inverse integer transform 4 times 4, inverse quantization 4 times 4. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 160 MHz in an ALTERA Stratix II FPGA. This architecture can process one macroblock (MB) for 432 clock cycles.

FPGA Codesign Implementation of Vector Directional Filter

Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator including VDF algorithm is implemented with fast pipelined architecture. The remaining parts were realized in software using NIOS II softcore processor and Clinux as operating system. Experimental results confirm that the use of hardware accelerator gives good results concerning image quality and filtering speed.

Perceptual Evaluation of JPEG2000

With the increasing usage of multimedia technologies, image compression requires higher performances as well as new features. To address these needs in the specific area of continuous tone still image encoding, a new standard is currently being developed, the JPEG2000. It is not only intended to provide rate-distortion and subjective image quality performance superior to existing standards, but also to provide new features and functionalities that current standards can either not address them efficiently or in many cases cannot address them at all. Copyright

A new method to implement a constant operand multiplier

In this paper we present a new method to implement constant operand multiplier. The structure is optimized in point of view of surface occupation and time execution. The principle of the new method based on a compression of four partial products into one row. The method proofs its availability for both signed and unsigned multiplication. Simulation results using FPGA implementation technology show an improvement of proposed algorithm performances compared to DADDA multiplier.

A digital control system based on codesign technology

In recent years, the ever-increasing capabilities of microelectronic devices allow the implementation of more sophisticated speed drives. The control structure performs a greater number and a wider range of functions. The difference in the nature of these functions pushed the designer to investigate the architecture on the hand, and the implementation on the other hand. A control system implemented on Codesign technology allows the use of the advantages of DSP in numerical calculation and FPGA in logical computation. The definition of system (FPGA and DSP) is reviewed and the reasons for this choice are discussed. The advantages of this technology are discussed as well as the difficulties encountered at the development stage.