N. N. Mahatme

Effects of Temperature and Supply Voltage on SEU- and SET-Induced Errors in Bulk 40-nm Sequential Circuits

The single-event sensitivity of bulk 40-nm sequential circuits is investigated as a function of temperature and supply voltage. An overall increase in SEU cross section versus temperature is observed at relatively high supply voltages. However, at low supply voltages, there is a threshold temperature beyond which the SEU cross section decreases with further increases in temperature. Single-event transient induced errors in flip-flops also increase versus temperature at relatively high supply voltages and are more sensitive to temperature variation than those caused by single-event upsets.

Effects of Total-Ionizing-Dose Irradiation on SEU- and SET-Induced Soft Errors in Bulk 40-nm Sequential Circuits

Synergetic effects of total-ionizing-dose irradiation on the single event upset (SEU) and single event transient (SET) performance of 40-nm sequential circuits are studied at doses up to 2 Mrad(SiO2). The impacts of input pattern and supply voltage are evaluated. An initial increase of SEU- and SET-induced soft error cross-section versus total dose is observed, followed by a decreasing trend at higher doses. The maximum increase of SEU- and SET-induced soft error cross-section occurs when the total-ionizing-dose is approximately 1.5 Mrad(SiO2) in the studied sequential circuit. The SET-induced soft error cross-section versus total dose increases at a faster speed than the SEU-induced soft error cross-section.

Effects of temperature and supply voltage on SEU- and SET-induced single-event errors in bulk 40-nm sequential circuits

Single event sensitivity of bulk 40-nm sequential circuits is investigated as a function of temperature and supply voltage. The temperature dependence of single event upsets is different for relatively high supply voltage and ultra-low supply voltage. Single-event-transient induced errors in flip-flops are more sensitive to temperature variation than single event upsets.

Analysis of temporal masking effect on single-event upset rates for sequential circuits

Reduction in single-event upset rates for sequential circuits due to temporal masking effect is evaluated. Effects of supply voltage, combinational-logic delay and particle LET are analyzed for sequential circuits SEU rates.

A critical re-examination of body-bias on the soft error rate and single-event latch-up in automotive SRAMs

Body-biasing is commonly used to regulate power/performance for modern integrated circuits. However, it has an additional soft error rate (SER) and single event latch-up (SEL) impact. The physics of bipolar action, charge collection mechanisms and drive current variation are explored to quantify the impact of body bias using a 90-nm technology. Results indicate that in certain cases body-biased operation can help achieve the elusive goal of lower power as well as lower SER and SEL. Practical design limits are proposed on the extent of well bias to achieve lower power and higher reliability, especially for high temperature automotive environments.

Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits

Reductions in single-event (SE) upset (SEU) rates for sequential circuits due to temporal masking effects are evaluated. The impacts of supply voltage, combinational-logic delay, flip-flop (FF) SEU performance, and particle linear energy transfer (LET) values are analyzed for SE cross sections of sequential circuits. Alpha particles and heavy ions with different LET values are used to characterize the circuits fabricated at the 40-nm bulk CMOS technology node. Experimental results show that increasing the delay of the logic circuit present between FFs and decreasing the supply voltage are two effective ways of reducing SE error rates for sequential circuits for particles with low LET values due to temporal masking. SEU-hardened FFs benefit less from temporal masking than conventional FFs. Circuit hardening implications for SEU-hardened and unhardened FFs are discussed.

Exploiting low power circuit topologies for soft error mitigation

Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.

Impact of particle LET on combinational logic single-event effects for advanced technologies

28-Nm planar, 20-nm planar, and 16-nm FinFET technology combinational and flip-flop circuits are investigated using different LET particles. An analytical model is developed to study the ratio of logic to flip-flop (FF) single-event (SE) cross-section as a function of LET particles. Results indicate that high-LET particles have a much stronger impact on the logic single-event (SE) cross-section as compared to the flip-flop (FF) SE cross-section for all three technology nodes.