Arthur F. Witulski

Charge Collection and Charge Sharing in a 130 nm CMOS Technology

Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hit node and adjacent nodes are quantified. Results show that for a twin-well CMOS process, PMOS charge sharing can be effectively mitigated with the use of contacted guard-ring, whereas a combination of contacted guard-ring, nodal separation, and interdigitation is required to mitigate the NMOS charge sharing effect for the technology studied

Comparison of resonant topologies in high-voltage DC applications

Because of their tolerance of transformer nonidealities, resonant converters are considered to be well-suited to high-voltage applications. The series and parallel resonant topologies, as well as a newly discovered hybrid resonant topology are compared for high-voltage applications. Design criteria which incorporate transformer nonidealities are developed and used in the construction of high voltage prototypes for each topology. It is found that the parallel topology leads to the lowest peak switch current and the most ideal behavior. >

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps in the 90-nm process. The increasing probability of longer SET pulses with scaling is a key factor determining combinational logic soft errors in advanced technologies. Mixed mode 3D-TCAD simulations demonstrate that the variation of pulse-width results from the variation in strike location.

Extension of state-space averaging to resonant switches and beyond

It is shown that the state-space averaging method can be extended by linear network theory from the domain of pulse-width-modulated converters to a much larger class of converters, including resonant switch converters, current programmed mode, and others. The canonical model concept is also extended, and it is shown that the effect of resonant switching is to introduce a feedback block into the generalized canonical model. These results are applied to linear zero-current and zero-voltage resonant switches, a novel class of nonlinear resonant switch converters, and the current programmed mode. Equivalent circuit models are developed for both full and half-wave operation, and experimental verification is presented. >

On-Chip Characterization of Single-Event Transient Pulsewidths

A new on-chip single-event transient (SET) test structure has been developed to autonomously characterize the widths of random SET pulses. Simulation results show measurement granularity of 900 ps for a 1.5 mum technology and also indicate that the measurement granularity rapidly scales down with technology. Laser tests were used to demonstrate circuit operation on test chips fabricated using a 1.5 mum process. The experimental results indicate pulsewidths varying from about 900 ps to over 3 ns as the laser energy was increased

HBD layout isolation techniques for multiple node charge collection mitigation

A three-dimensional (3D) technology computer-aided design (TCAD) model was used to simulate charge collection at multiple nodes. Guard contacts are shown to mitigate the charge collection and to more quickly restore the well potential, especially in PMOS devices. Mitigation of the shared charge collection in NMOS devices is accomplished through isolation of the P-wells using a triple-well option. These techniques have been partially validated through heavy-ion testing of three versions of flip-flop shift register chains.

Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Qcrit) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X ldquoprocess generationrdquo scaling penalty in area, speed, and power.

Introduction to modeling of transformers and coupled inductors

A tutorial paper is presented on modeling and design of transformers and coupled inductors. Beginning with a brief review of electromagnetic laws and magnetic circuit models, the magnetic and electric models of transformers and coupled inductors are developed, including both magnetizing and leakage effects. It is shown that while the voltage waveforms on the windings are primarily related by the turns ratio for both devices, the winding currents of transformers and coupled inductors are determined by very different mechanisms. An integrated structure with both transformer and coupled inductor on the same core is also discussed, as well as the special case of the coupled inductor used on a multiple-output transformer-isolated converter. >

Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology

Three-dimensional TCAD models are used in mixed- mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct hit ion strike. 130 nm and 90 nm technology are simulated. Results show careful well contact design can improve mitigation. However, well contact effectiveness is seen to decrease from the 130 nm to the 90 nm simulations.

Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

Circuit and 3D technology computer aided design mixed-mode simulations show that the single event upset vulnerability of 130- and 90-nm hardened latches to low linear energy transfer (LET) particles is due to charge sharing between multiple nodes as a result of a single ion strike. The low LET vulnerability of the hardened latches is verified experimentally.