N.P. van der Meijs

A 26

This paper presents an asynchronous SAR ADC for flexible, low energy radios. To achieve excellent power efficiency for a relatively moderate resolution, various techniques are introduced to reduce the power consumption: custom-designed 0.5 fF unit capacitors minimize the analog power consumption while asynchronous dynamic logic minimizes the digital power consumption. The variability of the custom-designed capacitors is estimated by a specialized CAD tool and verified by chip measurements. An implemented 8-bit prototype in a 90 nm CMOS technology occupies 228 μm × 240 μm including decoupling capacitors, and achieves an ENOB of 7.77 bit at a sampling frequency of 10.24 MS/s. The power consumption equals 26.3 μW from a 1 V supply, thus resulting in an energy efficiency of 12 fJ/conversion-step. Moreover, the fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6 nW. In that way, the energy efficiency of this converter can be maintained down to very low sampling rates.

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Abstract This paper discusses whether and how parasitic circuit elements must be included in the circuit simulator source file to obtain reliable simulation results. In particular, attention is paid to fabrication tolerances, wire capacitance (including fringing effects), wire resistance (dispersive line effects), coupling capacitances and capacitances associated with contacts and the aspect ratio of (non-rectangular) transistors.

W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios

An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. The paper proposes a boundary element method (BEM) for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification. In contrast to standard BE methods, we propose a Greens function which is specific to the domain and the problem. This allows minimal discretization and a direct extraction of circuit models for the cross-talk. The extraction can be combined with an efficient model reduction technique to obtain more simple, yet accurate models for the cross-talk. The complete extraction process has a linear time complexity and a constant memory usage. The method is fully implemented and integrated in an existing layout-to-circuit extractor.

Vlsi Circuit Reconstruction from Mask Topology

In this paper, we describe a method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits. Unlike numerical methods, that can be used for circuits containing only a few hundreds of substrate terminals, the new method can quickly extract circuits containing many thousands of substrate terminals. Examples are given that show that the method is sufficiently accurate for practical circuit verification. The method has been implemented in the layout-to-circuit extractor Space.

Extraction of circuit models for substrate cross-talk

For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a Boundary Element Method (BEM) can be used. The FEM is the most versatile and flexible whereas the BEM is faster, but requires a stratified, layout-independent doping profile for the substrate. Thus, the BEM is unable to properly model any specific, layout-dependent doping patterns that are usually present in the top layers of the substrate, such as channel stop layers. This paper describes a way to incorporate these doping patterns into our substrate model by combining a BEM for the stratified doping profiles with a 2D FEM for the top-level, layout-dependent doping patterns, thereby achieving improved flexibility compared to BEM and improved speed compared to FEM. The method has been implemented in the SPACE layout to circuit extractor and it has been successfully verified with two other tools.

Fast computation of substrate resistances in large circuits

We present an accurate and efficient method for extraction of parasitic capacitances in submicron integrated circuits. The method uses a 3-D finite element model in which the conductor charges are approximated by a piece-wise linear function on a web of edges located on the surface of the conductors. This yields a system of Greens function integral equations that is solved by a novel approximate matrix inversion technique that only utilizes the entries corresponding to pairs of finite elements that are physically close to each other. With N representing the size of the layout, this results in time and space complexities of O(N) and O(PIN) respectively. The method has been implemented in an efficient layout to circuit extractor and experimental results are presented.

Combined BEM/FEM substrate resistance modeling

Abstract In this paper the application of the boundary element method to the layout verification of VLSI designs is described. The methods for the calculation of interconnection capacitances and substrate resistances with the use of problem specific Greens functions are also described. The derivation of these functions for multilayer structures is presented. Emphasis is on computational efficiency and practical accuracy. These are achieved by the type of the Greens functions and an appropriate model reduction technique. The methods are implemented in the layout extractor Space.

An Efficient Finite Element Method for Submicron IC Capacitance Extraction

The authors describe a method to find RC models for (nonorthogonal) interconnections in VLSI layouts, including resistances as well as ground and coupling capacitances. The method starts with the construction of a finite-element mesh for the interconnection polygons. Resistances are assigned to the edges of the mesh, and capacitances to the vertices. Then, all internal nodes are eliminated by a novel and efficient node-reduction algorithm. This algorithm preserves the Elmore time constants between the remaining nodes, without actually computing them. The resulting network accurately reflects the electrical properties of the distributed RC interconnections, and can efficiently be simulated.<<ETX>>The authors describe a method to find RC models for (nonorthogonal) interconnections in VLSI layouts, including resistances as well as ground and coupling capacitances. The method starts with the construction of a finite-element mesh for the interconnection polygons. Resistances are assigned to the edges of the mesh, and capacitances to the vertices. Then, all internal nodes are eliminated by a novel and efficient node-reduction algorithm. This algorithm preserves the Elmore time constants between the remaining nodes, without actually computing them. The resulting network accurately reflects the electrical properties of the distributed RC interconnections, and can efficiently be simulated. >

Boundary element methods for 3D capacitance and substrate resistance calculations in inhomogeneous media in a VLSI layout verification package

This paper presents an algorithm that enables an extension of standard 3d capacitance extraction to take into account the effects of small dimensional variations of interconnects by calculating the corresponding capacitance sensitivities. By using an adjoint technique, capacitances and their sensitivities w.r.t. multiple geometric parameters can be obtained with one-time 3d extraction using the boundary element method (BEM).

Extracting simple but accurate RC models for VLSI interconnect

This paper presents a reduction technique that transforms large RC networks into a minimal admittance network between the terminals, and that at the same time preserves the moments of each admittance exactly, up to any desired order. Any RC network can be dealt with, including capacitive coupling between lines. The technique presented has been incorporated in an efficient layout-to-circuit extractor using a scanline approach. The extracted moments can be used either in combination with Pade approximants for detailed timing-analysis, or simple RC models can be obtained directly by fitting to the extracted moments. The main advantage over AWE is that nodes are eliminated on the fly, thus reducing memory usage up to an order of magnitude.