A.J. van Genderen

Extraction of circuit models for substrate cross-talk

An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. The paper proposes a boundary element method (BEM) for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification. In contrast to standard BE methods, we propose a Greens function which is specific to the domain and the problem. This allows minimal discretization and a direct extraction of circuit models for the cross-talk. The extraction can be combined with an efficient model reduction technique to obtain more simple, yet accurate models for the cross-talk. The complete extraction process has a linear time complexity and a constant memory usage. The method is fully implemented and integrated in an existing layout-to-circuit extractor.

Fast computation of substrate resistances in large circuits

In this paper, we describe a method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits. Unlike numerical methods, that can be used for circuits containing only a few hundreds of substrate terminals, the new method can quickly extract circuits containing many thousands of substrate terminals. Examples are given that show that the method is sufficiently accurate for practical circuit verification. The method has been implemented in the layout-to-circuit extractor Space.

An Efficient Finite Element Method for Submicron IC Capacitance Extraction

We present an accurate and efficient method for extraction of parasitic capacitances in submicron integrated circuits. The method uses a 3-D finite element model in which the conductor charges are approximated by a piece-wise linear function on a web of edges located on the surface of the conductors. This yields a system of Greens function integral equations that is solved by a novel approximate matrix inversion technique that only utilizes the entries corresponding to pairs of finite elements that are physically close to each other. With N representing the size of the layout, this results in time and space complexities of O(N) and O(PIN) respectively. The method has been implemented in an efficient layout to circuit extractor and experimental results are presented.

Boundary element methods for 3D capacitance and substrate resistance calculations in inhomogeneous media in a VLSI layout verification package

Abstract In this paper the application of the boundary element method to the layout verification of VLSI designs is described. The methods for the calculation of interconnection capacitances and substrate resistances with the use of problem specific Greens functions are also described. The derivation of these functions for multilayer structures is presented. Emphasis is on computational efficiency and practical accuracy. These are achieved by the type of the Greens functions and an appropriate model reduction technique. The methods are implemented in the layout extractor Space.

Extracting simple but accurate RC models for VLSI interconnect

The authors describe a method to find RC models for (nonorthogonal) interconnections in VLSI layouts, including resistances as well as ground and coupling capacitances. The method starts with the construction of a finite-element mesh for the interconnection polygons. Resistances are assigned to the edges of the mesh, and capacitances to the vertices. Then, all internal nodes are eliminated by a novel and efficient node-reduction algorithm. This algorithm preserves the Elmore time constants between the remaining nodes, without actually computing them. The resulting network accurately reflects the electrical properties of the distributed RC interconnections, and can efficiently be simulated.<<ETX>>The authors describe a method to find RC models for (nonorthogonal) interconnections in VLSI layouts, including resistances as well as ground and coupling capacitances. The method starts with the construction of a finite-element mesh for the interconnection polygons. Resistances are assigned to the edges of the mesh, and capacitances to the vertices. Then, all internal nodes are eliminated by a novel and efficient node-reduction algorithm. This algorithm preserves the Elmore time constants between the remaining nodes, without actually computing them. The resulting network accurately reflects the electrical properties of the distributed RC interconnections, and can efficiently be simulated. >

Reduced RC models for IC interconnections with coupling capacitances

The transmission behavior of interconnections in integrated circuits is often determined by their distributed RC effects. The authors present a modeling technique, for incorporation in a layout-to-circuit extraction program, that accurately represents these effects. The method consists of first replacing IC interconnections by a complex RC network and then transforming this complex RC network into a simple RC network. It extends previous work in that (1) besides preserving the Elmore time constants between the terminals of the interconnections, the method also preserves the total resistances between the terminals and the total capacitances, and (2) the method handles ground capacitances as well as coupling capacitances. >The transmission behavior of interconnections in integrated circuits is often determined by their distributed RC effects. The authors present a modeling technique, for incorporation in a layout-to-circuit extraction program, that accurately represents these effects. The method consists of first replacing IC interconnections by a complex RC network and then transforming this complex RC network into a simple RC network. It extends previous work in that (1) besides preserving the Elmore time constants between the terminals of the interconnections, the method also preserves the total resistances between the terminals and the total capacitances, and (2) the method handles ground capacitances as well as coupling capacitances.<<ETX>>

Delayed Frontal Solution for Finite-Element based Resistance Extraction

To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution method. We show that this method is inefficient when used with a scanline ordering of the elements. As an improvement, we introduce the Delayed Frontal Solution algorithm, which allows us to replace the scanline ordering by the minimumdegree ordering. Thus, extraction times are reduced with more than one order of magnitude at a small cost of extra memory.

Space-efficient extraction algorithms

A description is given of how the authors limited the space complexity of a layout to circuit extractor by: a combination of the scanline technique with the corner stitching technique; a region-based extraction algorithm; a judicious choice of netlist format; and a union-find data structure also supporting deletions of elements. The efficiency of the new algorithms and the resulting extractor is confirmed by experimental data. These results are important, since in practice the size of the largest design that can be handled is often hard-limited by available memory. >A description is given of how the authors limited the space complexity of a layout to circuit extractor by: a combination of the scanline technique with the corner stitching technique; a region-based extraction algorithm; a judicious choice of netlist format; and a union-find data structure also supporting deletions of elements. The efficiency of the new algorithms and the resulting extractor is confirmed by experimental data. These results are important, since in practice the size of the largest design that can be handled is often hard-limited by available memory.<<ETX>>

An efficient algorithm for analysis of non-orthogonal layout

A new algorithm for analysis of nonorthogonal layout is presented. The algorithm is a combination of the scanline and the corner stitching technique. It performs a directed enumeration of all tiles and pairs of abutting tiles that are retained only in a narrow band of adjustable width sweeping over the artwork. The enumeration provides a clean interface to many layout analysis tasks, such as design rule checking and circuit extraction. With N representing the size of the input, the expected-case time and space complexities of the algorithm are O(N) and O( square root N), respectively.<<ETX>>A new algorithm for analysis of nonorthogonal layout is presented. The algorithm is a combination of the scanline and the corner stitching technique. It performs a directed enumeration of all tiles and pairs of abutting tiles that are retained only in a narrow band of adjustable width sweeping over the artwork. The enumeration provides a clean interface to many layout analysis tasks, such as design rule checking and circuit extraction. With N representing the size of the input, the expected-case time and space complexities of the algorithm are O(N) and O( square root N), respectively. >

Coherent interconnect/substrate modeling using SPACE - an experimental study

The functionality of modern ICs increasingly suffers from substrate noise. Digital transistors switching at high frequencies are known to induce substrate noise through their bulk contacts. In addition, interconnects carrying aggressive, high-frequency signals are known to induce substrate noise through their capacitive coupling with the substrate. In this paper, we describe how our layout-to-circuit extractor SPACE builds a coherent interconnect/substrate model from a layout. The result is a comprehensive circuit model which can immediately be simulated by a regular circuit simulator. We evaluate our modeling approach by extracting a ring-oscillator layout and simulating the resulting circuit with HSPICE. We have done extractions, under varying conditions; the simulation results give practical insight into relevant substrate noise phenomena.