N. Tran

Wireless technologies for closed-loop retinal prostheses

In this paper, we discuss various technologies needed to develop retinal prostheses with wireless power and data telemetry operation. In addition to the need to communicate with the implanted device, supply of power to the retinal prosthesis is especially difficult. This is because, in the implanted state, the device is not fixed in position due to constant motion of the eye. Furthermore, a retinal prosthesis incorporating a high density electrode array of more than 1000 electrodes is expected to consume approximately 45 mW of power and require 300 kbps of image and stimulation data. The front end of the wireless power and data transmission, the antenna, needs to be small compared to the size of the eye. Also, the wireless module is expected to operate in the reactive near-field region due to small separation between the transmit and receive antennas compared to their size and corresponding operating wavelength. An inductive link is studied as a means to transfer power and for data telemetry between the implant and external unit. In this work, the use of integrated circuit and microfabrication technologies for implementing inductive links is discussed. A closed-loop approach is taken to improve performance and reach optimum operation condition. Design and simulation data are presented as the basis for development of viable wireless module prototypes.

A Complete 256-Electrode Retinal Prosthesis Chip

This paper presents a complete 256-electrode retinal prosthesis chip, which is small and ready for packaging and implantation. It contains 256 separate programmable drivers dedicated to 256 electrodes for flexible stimulation. A 4-wire interface is employed for power and data transmission between the chip and a driving unit. Power and forward data are recovered from a 600 kHz differential signal, while backward data are sent at 100 kbps rate simultaneously. The stimulator possesses many stimulation features, supporting various stimulation strategies. Many safety features are included such as real-time monitoring of voltage compliance and temperature, electrode self-locking in the event of out-of-compliance, and ESD protection circuit at every electrode. The chip is fabricated in a 65 nm CMOS process. The electrode driver pitch is 150 μm, and total chip area is 8 mm 2 . The chip has been extensively tested and all the requirements have been successfully verified. The measured DC current error for single driver stimulation without electrode shorting is 20 nA. The average power consumption per electrode with typical stimulus pulse parameters and full-scale output current is 129 μW, inclusive of all standby power. The chip overall power efficiency is 70% with 23 mW of power delivered to load.

A fully flexible stimulator using 65 nm cmos process for 1024-electrode epi-retinal prosthesis

This paper presents a fully flexible stimulator using 65 nm CMOS process for a 1024-electrode epi-retinal prosthesis. The stimulator can select any number of electrodes at any time and also supports both mono-polar and multi-polar stimulation. Furthermore, the stimulator supports a wide range of stimulus parameters. A novel feature is that the electrode driver operates in an alternately pull-push manner, which helps reduce headroom voltage while guaranteeing charge balance at the active electrode. The use of positive supplies instead of both positive and negative supplies simplifies CMOS circuit design. The current distribution between two nearby simultaneously active electrode groups was investigated and measurement result showed a maximum current crosstalk of 8%.

A prototype 64-electrode stimulator in 65 nm CMOS process towards a high density epi-retinal prosthesis

This paper presents a highly flexible 64-electrode stimulator using 65 nm CMOS process fabricated as a stage towards a 1024-electrode epi-retinal prosthesis, which aims to restore partial vision in patients suffering from eye diseases such as retinitis pigmentosa (RP) and age-related macular degradation (AMD). The stimulator drives 64 electrodes with many flexible features, which are necessary before making a complete 1024-electrode implant chip. Each electrode driver can provide a bi-phasic stimulus current with fully programmable parameters such as amplitude, pulse duration, inter-phase gap, and stimulation rate. The electrode driver operates in an alternately pull-push manner with only one current source working at a time, which helps reduce headroom voltage while controlling charge balance at the active electrode. The stimulator varies both stimulus current amplitude and stimulation rate to represent phosphene brightness. The stimulus current amplitude starts from the tissue depolarization threshold with 64 different levels. The selection of active and return electrodes is arbitrary, any electrodes and any number of them can be selected at any time. The power consumption of the stimulator is 400 μW excluding the stimulus power. Measurement results verify correct operation. The stimulator is easily scaled up to drive 1024 electrodes.

A super low power MICS band receiver in 65 nm CMOS for high resolution epi-retinal prosthesis

We report a super low power MICS band receiver for a high resolution epi-retinal prosthesis (BionicEye). The FSK receiver consumes less than 1.5 mW power with 1 V supply. It can achieve a maximum data rate of 400 kb/s. In this paper, we present the research work carried out on designing a fully-integrated sub-threshold receiver fabricated on a 65nm CMOS chip. In order to achieve super low power consumption, more than 90% of the transistors in all analog building blocks are operated in sub-threshold region. System level issues, such as required receiver architecture and specifications are also addressed1.

Design of a compact ultra wideband balanced-to-balanced power divider/combiner

A compact ultra wideband balanced-to-balanced power divider/combiner based on Finite Ground Coplanar Waveguide (FGCPW) phase inverter is presented. By replacing the λ/2 transmission lines in [1] by FGCPW phase inverters, circuit size of the power divider/combiner has been significantly reduced, from (0.75λ × 0.5λ) to about (0.375λ × 0.125λ). With the wideband property of the FGCPW phase inverter, 3-dB fractional bandwidth of the proposed power divider/combiner can be obtained up to 200%. A -3.7 dB differential-mode transmission coefficient |SddAB| and -0.25 dB common-mode reflection coefficients |SccAA|, |SccBB| have been obtained. Other mixed mode S-parameters are all less than -10 dB from 0.1 GHz to 1.75 GHz. The measurement results agreed well with the simulation results.

A super low power MICS band receiver front-end down converter on 65 nm CMOS

This paper presents a super low power MICS band receiver front-end down converter on 65 nm CMOS for implantable biomedical devices. This down converter, including a LNA and a quadrature mixer, only consumes 500 µA DC current under 1 V supply. With a small LO swing of 300 mV, it provides a voltage conversion gain of 35 dB and a noise figure of 7.4 dB, while a −20 dBm IIP3 is obtained. In order to achieve super low power, current-reuse structure is adopted and all transistors are operated in deep sub-threshold region. Circuits level issues and techniques are also discussed.

A precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrodes retinal prosthesis

In this paper, we present a precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrode retinal prosthesis. Our stimulator is based on current mode stimulation. To generate a precisely matched biphasic current pulse, a dynamic current copying technique is applied at the stimulator front-end. A compliance voltage monitoring circuitry is included at the stimulator front-end to detect if a voltage across electrode-tissue interface goes beyond a predefined compliance voltage. Simulation results show the mismatch of a biphasic current pulse (at a maximum stimulation current of 476μA) is less than 0.1%. Also, the stimulator issues alarm signals, when a voltage compliance occurs during stimulation due to high tissue impedance. Our stimulator is implemented using a 65nm low voltage (LV) CMOS process, which helps reducing implementation area and power consumption.

A charge-balanced 4-wire interface for the interconnections of biomedical implants

This paper presents a charge-balanced 4-wire interface on medical platinum wires for biomedical implants. This interface was originally designed to deliver power and full duplex data between implanted units of a retinal prosthesis. Detailed circuits on both sides of the wire interface are depicted. The proposed method ensures the total electrical charge is balanced over time within the implant to avoid the risk of harmful irreversible electrochemical reactions. Experiments show that the data links using this 4-wire interface design has minimal Bit Error Rate (BER) and very low cost in terms of power and area consumptions. The forward data recovery consumes 300 μW at 600 kbps with an area of 15×200 μm2 in 65nm CMOS. The backward data encoding circuit requires an average current of a mere 3 μA at 100 kbps while its area is 15×140 μm2.

A ultra low power, wide input range MICS band channel selection filter on 65 nm CMOS

This paper proposes a low power MICS band receiver channel selection filter on 65 nm CMOS for implantable biomedical devices. This 5th-order elliptic OTA-C bandpass filter utilizes sub-threshold inverter based OTAs. In order to broaden input range of the filter, the first OTA stage is linearized by using the active-error feedforward technique. The overall filter only consumes 300 μA DC current under 1 V supply, while having an input range up to 0.6 Vpp. The total harmonic distortion (THD) is −58 dB for 1.3 MHz input signal at 0.5 Vpp swing. As a MICS band channel selection filter, it has 300 kHz bandwidth and exhibits more than 45 dB attenuation to the ajacent channel. By using NFET capacitors as OTAs, load, the chip area of this filter is minimized.