Hosung Chun

A Complete 256-Electrode Retinal Prosthesis Chip

This paper presents a complete 256-electrode retinal prosthesis chip, which is small and ready for packaging and implantation. It contains 256 separate programmable drivers dedicated to 256 electrodes for flexible stimulation. A 4-wire interface is employed for power and data transmission between the chip and a driving unit. Power and forward data are recovered from a 600 kHz differential signal, while backward data are sent at 100 kbps rate simultaneously. The stimulator possesses many stimulation features, supporting various stimulation strategies. Many safety features are included such as real-time monitoring of voltage compliance and temperature, electrode self-locking in the event of out-of-compliance, and ESD protection circuit at every electrode. The chip is fabricated in a 65 nm CMOS process. The electrode driver pitch is 150 μm, and total chip area is 8 mm 2 . The chip has been extensively tested and all the requirements have been successfully verified. The measured DC current error for single driver stimulation without electrode shorting is 20 nA. The average power consumption per electrode with typical stimulus pulse parameters and full-scale output current is 129 μW, inclusive of all standby power. The chip overall power efficiency is 70% with 23 mW of power delivered to load.

Implantable stimulator for bipolar stimulation without charge balancing circuits

It is critically important to maintain charge balance in neural stimulation, employing biphasic current pulses. Any mismatch in biphasic current pulses will result in charge imbalance, possibly leading to tissue damage. In this paper, we propose an implantable stimulator for bipolar stimulation to minimize the mismatch of biphasic current pulses, without dc blocking capacitors or charge balancing circuits. Using 0.35μm HV CMOS process with 20V power supply, the maximum mismatch between cathodic and anodic current is achieved less than 0.4μA out of full scale current of 1mA. (equivalent to 11 bit accuracy at 1mA) Residual dc current of less than 1nA is achieved with shorting enabled, under 0.1ms stimulation for each cathodic and anodic phase out of 3ms period.

CMOS current reference generator using integrated resistors

A novel method is proposed that can generate a stable reference current using on-chip integrated resistors without the use of trimming. By optimally combining different types of integrated resistors, the overall resistance variability is reduced below that of the most accurate available resistor. Combining such a resistance with a band-gap reference and a temperature compensation circuit, we implement an on-chip current reference. This circuit is implemented using a standard 0.35um CMOS process with 3V power supply. Monte-Carlo simulations show a nominal reference current (1uA) from a combined resistor varies by ±11.5% over a −10°C to 70°C temperature range. This variation is reduced by a factor of two compared with using a normal resistor. The measured values of the combined resistor and the normal resistor are 1.08MΩ and 1.45MΩ, respectively. This is −10% and +20% deviation from the desired value of 1.2MΩ.

Power saving design techniques for implantable neuro-stimulators

Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. Second, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. In combination, significant implant power consumption reduction is achieved.

Dual-Stacked Current Recycling Linear Regulators With 48% Power Saving for Biomedical Implants

This paper demonstrates a dual-stacked current recycling linear power supply circuit for biomedical implants. Implantable neuro-stimulators often require high-voltage power supplies for electrode actuation purposes while most of the electronic implant sub-systems require low-voltage supplies which are often generated by linear regulators with poor power efficiency. The proposed current recycling technique and circuit allow linear regulators to be stacked, dividing the high-voltage power supply into two low-voltage supply domains; current can be recycled between these two power supplies and power efficiency in the low-voltage powered circuits can be close to doubled. The power supply circuit is implemented in 0.35 μm high-voltage CMOS process and occupies an active silicon area of 0.45 mm2 , achieving maximum power saving factor and current efficiency of 48.6% and 97.2%, respectively, with quiescent current of only 45 μA.

A precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrodes retinal prosthesis

In this paper, we present a precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrode retinal prosthesis. Our stimulator is based on current mode stimulation. To generate a precisely matched biphasic current pulse, a dynamic current copying technique is applied at the stimulator front-end. A compliance voltage monitoring circuitry is included at the stimulator front-end to detect if a voltage across electrode-tissue interface goes beyond a predefined compliance voltage. Simulation results show the mismatch of a biphasic current pulse (at a maximum stimulation current of 476μA) is less than 0.1%. Also, the stimulator issues alarm signals, when a voltage compliance occurs during stimulation due to high tissue impedance. Our stimulator is implemented using a 65nm low voltage (LV) CMOS process, which helps reducing implementation area and power consumption.

A charge-balanced 4-wire interface for the interconnections of biomedical implants

This paper presents a charge-balanced 4-wire interface on medical platinum wires for biomedical implants. This interface was originally designed to deliver power and full duplex data between implanted units of a retinal prosthesis. Detailed circuits on both sides of the wire interface are depicted. The proposed method ensures the total electrical charge is balanced over time within the implant to avoid the risk of harmful irreversible electrochemical reactions. Experiments show that the data links using this 4-wire interface design has minimal Bit Error Rate (BER) and very low cost in terms of power and area consumptions. The forward data recovery consumes 300 μW at 600 kbps with an area of 15×200 μm2 in 65nm CMOS. The backward data encoding circuit requires an average current of a mere 3 μA at 100 kbps while its area is 15×140 μm2.

A low-power, small-area and programmable bandgap reference

In this paper, we present a low-power, small-area and programmable bandgap reference, based on the reverse bandgap reference concept. It is implemented in a 65nm digital CMOS process with 1.2V power supply. It employs two switched capacitor amplifiers to weight temperature dependent voltages with opposite polarity. Programmability is achieved by adjusting a closed-loop gain of these two amplifiers. The implemented BGR generates three reference voltages, such as 0.591V (V_REF1), 0.872V (V_REF2) and 1.189V (V_REF3). In simulation, with ±10% supply voltage variation, the temperature coefficient (TC) of V_REF1, V_REF2 and V_REF3 is less than 43ppm/°C, 28ppm/°C and 33ppm/°C, respectivley, in the temperature range from -40°C to 100°C. The average power consumption is less than 40μW for V_REF1, 60μW for V_REF2 and 110μW for V_REF3. The layout area (excluding bonding pads) is 200μm by 190μm.

POWER SAVING CIRCUIT DESIGN TECHNIQUES FOR IMPLANTABLE NEURO-STIMULATORS

Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. Second, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. A variation of this include passive charge recovery for further power reduction. In combination, significant implant power consumption reduction is achieved.

Design of reliable current recycling linear regulators for biomedical implants

A novel linear regulating power supply circuit with our unique current recycling technique for biomedical implants is proposed in this paper. In implantable neural stimulation systems, besides high-voltage actuation power supplies dedicated to stimulation electrodes, a number of low-voltage power supplies generated by linear regulators are often required for efficient electronic system operations. We design a stacked dual linear regulating power supply with full considerations of process variations and mismatch in 0.35 µm high-voltage CMOS process and Monte Carlo simulation results demonstrate power supplies with less than 6.2% of variation on low voltage power rails and a power saving factor as well as current efficiency up to 48.8% and 97.6% respectively are achieved.